According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

An array substrate, a display panel, and a fabrication method of the array substrate are provided. The array substrate comprises a first thin film transistor including a metal oxide thin film transistor, and a second thin film transistor including an amorphous silicon thin film transistor. The first thin film transistor and the second thin film transistor are disposed above a substrate. The first thin film transistor is located in a display region of the array substrate, and the second thin film transistor is located in a peripheral circuit region of the array substrate.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

A display device including: a first base substrate including a display area and a non-display area adjacent to the display area; a plurality of signal lines disposed in the display area; a plurality of pixels disposed in the display area and connected to the signal lines; and a driving circuit disposed in the non-display area and configured to provide driving signals to the signal lines. Each of the pixels includes a switching transistor connected to a corresponding signal line, and a display element connected to the switching transistor.

The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor device including a capacitor and a transistor is provided. In the semiconductor device, the transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitor, and the capacitor includes a first electrode that is electrically connected to the transistor.

The present disclosure discloses an organic light emitting display and a method of manufacturing the same. The manufacturing method includes: forming a gate electrode of a first thin film transistor (TFT) on a substrate; forming a first insulating combination layer, and a source electrode and a drain electrode of the first TFT, a source electrode and a drain electrode of a second TFT and a first storage electrode of a storage capacitor located on the first insulating combination layer continuously; forming a third insulating layer on the first insulating combination layer, the source electrode and the drain electrode and the first storage electrode; forming the gate electrode of the second TFT and a second storage electrode of the storage capacitor on the third insulation layer; forming a second insulating combination layer on the third insulating layer; and forming a through hole in the second insulation combination layer.

Disclosed is a display device that may include a GIP circuit, provided on a display area of a substrate, for supplying gate signals to gate lines, wherein the GIP circuit includes a thin film transistor provided in the boundaries between adjacent pixels.

The present invention provides a display panel and a display device. In the display panel, edges of multiple rows of pixel units are arranged in a step-like manner, each row of pixel units include a central pixel unit and a marginal pixel unit, each central pixel unit includes first thin film transistors each corresponding to a sub-pixel and having a first semiconductor region; each marginal pixel unit includes second thin film transistors each corresponding to a sub-pixel and having a second semiconductor region; length and width of the first semiconductor region are respectively set to be a first set length and a first set width, length and width of the second semiconductor region are respectively set to be a second set length and a second set width such that brightness of the marginal pixel unit is smaller than brightness of the central pixel unit during display.

A pixel array substrate including a substrate having at least one via, at least one conductor disposed in the at least one via, pixel units, scan lines electrically connected to the pixel units, at least one shift register and at least one bus line is provided. The pixel units, the scan lines and the at least one shift register are disposed on a first surface of the substrate. The at least one shift register is used to transmit a first gate signal to the corresponding scan lines. The at least one bus line is disposed on a second surface of the substrate. The at least one bus line is electrically connected to the at least one shift register by the at least one conductor.