An electronic device of an embodiment of the disclosure includes a first substrate, a second substrate, and a driving layer. The first substrate and the second substrate are disposed opposite to each other, and the driving layer is disposed between the first substrate and the second substrate. The driving layer includes a scan line and a data line. The scan line is disposed on the first substrate and includes a first scan line segment. The first scan line segment has an opening and includes a first branch and a second branch. The first branch and the second branch are located on two opposite sides of the opening and are electrically connected in parallel with each other. The data line is disposed on the first substrate and intersects with the scan line. The electronic device of the embodiment of the disclosure may exhibit ideal display effect.

A semiconductor structure is provided having improved electrostatic contact close to the dielectric pillar that separates a first device region from a second device region. The semiconductor structure includes a dielectric pillar located between a first vertical nanosheet stack of suspended semiconductor channel material nanosheets and a second vertical nanosheet stack of suspended semiconductor channel material nanosheets. Horizontal dielectric bridge structures can be located in the first and second device regions. The horizontal bridge structures connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar. A dielectric spacer structure can laterally surround a lower portion of the dielectric pillar and be present in a semiconductor substrate. In some embodiments, the horizontal dielectric bridge structures can be omitted.

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate, a semiconductor structure, a gate dielectric layer, and a first gate. The semiconductor structure is disposed above the substrate and includes two thick portions and a thin portion located between the two thick portions. A thickness of the two thick portions is larger than a thickness of the thin portion. The gate dielectric layer is disposed on the semiconductor structure. The first gate is disposed on the gate dielectric layer. A width of the first gate is smaller or equal to a width of the thin portion, and the first gate is overlapped with the thin portion in a normal direction of a top surface of the substrate. A doping concentration of the two portions is larger than a doping concentration of the thin portion.

A semiconductor device in which variation of characteristics is small is provided. A second insulator, an oxide, a conductive layer, and an insulating layer are formed over a first insulator; a third insulator and fourth insulator are deposited to be in contact with the first insulator; a first opening reaching the oxide is formed in the conductive layer, the insulating layer, the third insulator, and the fourth insulator; a fifth insulator, a sixth insulator, and a conductor are formed in the first opening; a seventh insulator is deposited over the fourth insulator, the fifth insulator, and the sixth insulator; a mask is formed in a first region over the seventh insulator in a top view; oxygen is implanted into a second region not overlapping the first region in the top view; heat treatment is performed; a second opening reaching the fourth insulator is formed in the seventh insulator; and heat treatment is performed.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

A semiconductor device that has reduced power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first circuit including a first transistor and a first FTJ element, and a second circuit including a second transistor and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, and a first terminal of the second transistor is electrically connected to an input terminal of the second FTJ element. A second terminal of the first transistor and a second terminal of the second transistor are electrically connected to a read circuit. In a data writing method, a voltage is applied between the input terminal and the output terminal of each of the first FTJ element and the second FTJ element to polarize the first FTJ element and the second FTJ element. In a data reading method, a differential current flowing through the first FTJ element and the second FTJ element is input to the read circuit.