A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.

As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

The present disclosure provides a thin film transistor and a manufacturing method therefor, an array substrate, and a display panel. The thin film transistor includes a substrate and an active layer and a first gate electrode both located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the second film layer has a lower mobility than the first film layer, and the second film layer has a larger density than the first film layer.

The present disclosure provides a field effect transistor and a method for manufacturing the same, and a display panel, relating to the field of display technologies. The field effect transistor includes a substrate, an active layer, a source, a drain, a first insulating layer and an oxygenating layer. An orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of a target region of the active layer on the substrate. Therefore, when the oxygenating layer is prepared, oxygen elements in the process environment can diffuse to the target region of the active layer, to oxygenate the active layer. In this way, oxygen vacancies in the active layer can be reduced, and the uniformity and stability of the active layer is improved, thereby further improving the performance of the field effect transistor.

The present disclosure provides a thin film transistor comprising a gate electrode, an active layer, a source electrode, and a drain electrode, wherein the active layer includes a first channel part overlapping the source electrode, a second channel part overlapping the drain electrode, and a connection part connecting the first channel part and the second channel part, and the connection part is a conductorized region. Additionally, a manufacturing method of the thin film transistor and a display apparatus including the thin film transistor mentioned above are disclosed.

A stacked vertical TFT is provided. Such a stacked vertical TFT may comprise a source electrode, a drain electrode, and a gate electrode between the source electrode and the drain electrode. The source electrode, the gate electrode, and the drain electrode may be arranged on top of one another on vertically separated planes in a stacked arrangement. A semiconductor layer may be provided that at least partially surrounds the stacked arrangement and permits the flow of current carriers from the source to the drain. The source electrode, the gate electrode, and the drain electrode may comprise patterned electrodes. The source electrode, the gate electrode, and the drain electrode comprise identical patterned electrodes. The identical patterned electrodes may be aligned with one another. The patterned electrodes may take the form of perforations or of a comb-like structure.