The present invention provides a pixel unit and an array substrate. The pixel electrode includes four branch sections to divide the pixel zone into four display domains, helping improve the large angle color shifting problem of a display product and also simplifying the structure of the pixel electrode and making the manufacturing process simple, and facilitating the production of large-size wide-angle display products. The array substrate of the present invention is composed, in the horizontal direction, of multiple pixel units. The pixel units each include a pixel electrode that includes four branch sections to divide the pixel zone into four display domains, helping improve the large angle color shifting problem of a display product, and the pixel electrode has a simple structure to simplify the manufacturing process and facilitate the production of large-size wide-angle display products.

A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled.

The invention provides a method for manufacturing a TFT substrate and a TFT substrate manufactured thereof. In the above TFT substrate, the low temperature poly-silicon layer is produced by solid phase crystallization, the cost of production is under budget, and the TFT substrate is a double-grid structure that can guarantee the electrical characteristics of the thin film transistor and better the capacity of drive, and leakage phenomenon caused by groove light seldom happens.

An array substrate is provided. The array substrate includes: a substrate; a LTPS TFT disposed above the substrate; a planarization layer covering the LTPS TFT; a via hole formed in the planarization layer, wherein the via hole reveals a drain electrode of the LTPS TFT; multiple common electrodes and receiving electrodes disposed separately on the planarization layer, wherein the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other; a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole. A manufacturing method for the array substrate is also provided. The present invention can reduce one manufacturing process and decrease production cost.

A thin-film transistor substrate and a display device comprising the same are provided which can improve display quality by reducing or preventing deterioration of the characteristics of thin-film transistors. The thin-film transistor substrate comprises thin-film transistors on a lower protective metal layer. Each thin-film transistor comprises a buffer layer, a semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a source electrode and a drain electrode, and a first electrode. The lower protective metal layer is electrically connected to the gate electrode and overlaps the channel region of the semiconductor layer.

A display panel including a first substrate, a second substrate and a display medium is provided. The first substrate includes a base substrate, a gate, an active layer, a source, a drain, and a shielding structure. The gate is disposed on the base substrate. The active layer is electrically insulated from and disposed correspondingly to the gate. The source and the drain are electrically connected to the active layer. The shielding structure is disposed on the active layer and overlaps with at least part of the active layer. The shielding structure includes a metal layer and a metal oxide or metal nitride layer. The shielding structure is electrically insulated from the source. The display medium is disposed between the first substrate and the second substrate.

An array substrate includes a substrate and data lines and scan lines arranged on the substrate. The data lines and the scan lines define plural pixel regions. A thin film transistor is arranged in each pixel region and includes a gate electrode, a source electrode, a drain electrode, and an active region. The gate electrode is arranged above the active region. The source electrode and the drain electrode are arranged at two opposite sides of the active region respectively. A light shielding metal layer is further arranged in each pixel region. The light shielding metal layer and the data lines are arranged in the same layer on the substrate. The light shielding metal layer is arranged under the active region and at least partially overlaps with the active region. The data line is close to the source electrode and does not overlap with the active region at least partially.

An electro-optical device includes a first light shielding film; a transistor element formed on the first light shielding film to overlap the first light shielding film; a second light shielding film formed on the transistor element to overlap the transistor element and electrically connected to an input terminal of the transistor element; a transparent conductive film extended toward an upper layer side of the second light shielding film in an opening region, through which light penetrates, of the display region; a dielectric film formed on the transparent conductive film in the opening region; and a transparent pixel electrode formed on the dielectric film in the opening region, constituting a storage capacitor together with the transparent conductive film and the dielectric film, and having a transparent pixel electrode which is electrically connected to the transistor element.

The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate according to the present invention forms a gate electrode in the same metal layer with source and drain electrodes and divides a common electrode layer that is conventionally in the form of an entire surface into two portions, of which one serves as a common electrode, while the other portion feeds an input of a gate scan signal thereby eliminating an operation of forming an interlayer insulation layer and thus reducing manufacturing cost of the operation. The array substrate of the present invention comprises a gate electrode that is formed in the same metal layer with source and drain electrodes so that no interlayer insulation layer is present between the gate electrode and the source and drain electrodes, thereby simplifying the structure and reducing the manufacturing cost of the array substrate.

A thin film transistor array substrate includes a bottom gate disposed on a substrate and a bottom gate insulating layer covering the bottom gate, a semiconductor oxide layer disposed on the bottom gate insulating layer and an etch blocking layer covering the semiconductor oxide layer and including a first via, a drain disposed on the etch blocking layer and contacting with the semiconductor oxide layer through the first via and an insulating protection layer covering the drain, a second via arranged in the insulating protection layer, the etch blocking layer and the bottom gate insulating layer, a top gate disposed on insulating protection layer and contacting with the bottom gate through the second via. A method for manufacturing the thin film transistor array substrate is also disclosed. The thin film transistor prevents the threshold voltage thereof from being drifted in a case of negative bias illumination stress (NBIS).