A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Embodiments of the present disclosure relate to a multi-function circuit. The circuit comprises a low side circuit that is comprised with a first set of enhancement mode transistors. The half bridge circuit also includes a high side circuit that is comprised of a second set of transistors. Each of the enhancement mode transistors of the first set and second set of enhancement mode transistors are Gallium Nitride (GaN) transistors. In some embodiments, the GaN transistors are High Electron Mobility Transistors (HEMTs). In additional embodiments, the GaN transistors are configured and operated as saturated switches. In further embodiments, the half bridge circuit is designed as a discrete circuit. Additionally, each of the first set and second set of transistors, diodes, resistors, and all passive elements are discrete components arranged to form a half bridge circuit. In fact, the entire half bridge circuit is built from discrete components.

A detection circuit includes an under-voltage circuit. The under-voltage circuit includes a first GaN high electron mobility transistor (HEMT) configured to operate as both a voltage comparator and a voltage reference. The detection circuit can also include an over-voltage detection circuit. The over-voltage detection circuit includes a second GaN HEMT that is also configured to operate as both a voltage comparator and a voltage reference. Each of the under-voltage circuit and over-voltage circuit includes a GaN HEMT logic inversion element to provide electrical hysteresis. Also, the under-voltage detection circuit and the over-voltage detection circuit are configured to provide outputs to a single power good terminal. The first GaN HEMT can be configured to use its gate source threshold voltage for voltage comparison and reference. The second GaN HEMT can be configured to use its gate source threshold voltage for voltage comparison and reference.

A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers.

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate.

A superlattice composite structure includes a first superlattice stack layer and a second superlattice stack layer. The first superlattice stack layer includes a plurality of first units stacked along a vertical direction. Each of the first units includes an aluminium nitride (AlN) layer, an aluminium gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer stacked in sequence along the vertical direction. The second superlattice stack layer is stacked with the first superlattice stack layer along the vertical direction. The second superlattice stack layer includes a plurality of second units stacked along the vertical direction. Each of the second units includes another AlN layer, another AlGaN layer and another GaN layer stacked in sequence along the vertical direction.

A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.