Embodiments provide a quantum well device and the method for forming this device with high mobility and higher punch through voltages. For forming the quantum well device, a buffer layer can be formed on a patterned substrate of a quantum well device. A fin-like structure can be formed through an etching process performed to the buffer layer. A quantum well layer, a barrier layer, a cover layer and a dielectric layer can be successively deposited on the buffer layer and surface of the fin-like structure. A metal layer can then be formed on the surface of the said dielectric layer. Metal gate electrode and gate dielectric layer can be formed on the metal layer and dielectric layer. The cover layer, the barrier layer and the quantum well can then be etched to form recessed source and drain regions. Such a quantum well device can have better performance and reliability.

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

A field effect diode comprises: a substrate; a nucleation layer, a back barrier layer, a channel layer, a first barrier layer and a second barrier layer sequentially located on the substrate; and an anode and a cathode located on the second barrier layer, wherein a groove is formed in the second barrier layer, two-dimensional electron gas is formed at an interface between the first barrier layer and the channel layer except for a part of the interface under the groove when a reverse bias voltage or no external voltage is applied to the field effect diode, and is formed at all parts of the interface when a forward bias voltage is applied to the field effect diode.

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a N-type field-effect transistor positioned in the semiconductor substrate, and a P-type field-effect transistor positioned in the semiconductor substrate and spaced apart the N-type field-effect transistor. N-type field-effect transistor includes a first germanium nanowire, a first III-V compound layer surrounding around the first germanium nanowire, a first potential barrier layer mounted on the first III-V compound layer, a first gate dielectric layer, a first gate, a first source region and a first drain region mounted on two sides of the first gate. P-type field-effect transistor includes a second germanium nanowire, a second III-V compound layer surrounding around the second germanium nanowire, a second potential barrier layer mounted on the second III-V compound layer, a second gate dielectric layer, a second gate, a second source region and a second drain region mounted on two sides of the second gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and the P-type and N-type field-effect transistors are gate-surrounding devices to enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

A semiconductor device employs an epitaxial layer arrangement including a first ohmic contact layer and first modulation doped quantum well structure disposed above the first ohmic contact layer. The first ohmic contact layer has a first doping type, and the first modulation doped quantum well structure has a modulation doped layer of a second doping type. At least one isolation ion implant region is provided that extends through the first ohmic contact layer. The at least one isolation ion implant region can include oxygen ions. The at least one isolation ion implant region can define a region that is substantially free of charge carriers in order to reduce a characteristic capacitance of the device. A variety of high performance transistor devices (e.g., HFET and BICFETs) and optoelectronic devices can employ this device structure. Other aspects of wavelength-tunable microresonantors and related semiconductor fabrication methodologies are also described and claimed.

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.