A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and the fin structure includes a plurality of nanostructures stacked in a vertical direction. The semiconductor device structure includes a gate structure formed over the fin structure, and an S/D structure formed adjacent to the gate structure. The semiconductor device structure includes a first via formed adjacent to the S/D structure, and a first contact structure formed over the S/D structure. The semiconductor device structure includes a second contact structure formed below the S/D structure, and the first via is in direct contact with the first contact structure and the second contact structure.

A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

A semiconductor device is provided. The semiconductor device includes an active region, a gate, a gate contact formed on the gate, the gate contact overlapping in plan view with at least a portion of the active region, and a source/drain contact formed on the active region and adjacent to the gate contact. The gate contact is offset from a centerline of the gate in a direction away from the source/drain contact.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

Semiconductor devices with a source contact extending into a substrate are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate stack is disposed over the barrier layer in the gate region. A source contact in the source region extends into the semiconductor substrate, including a first contact with a 2DEG in the heterojunction structure and a second contact with the semiconductor substrate.

A semiconductor device may include a first substrate, a lower pattern on a first side of the first substrate, a plurality of sheet patterns on the lower pattern and spaced apart from each other in a first direction, a gate electrode which surrounds portions the plurality of sheet patterns, a source/drain pattern which is on one side of the gate electrode and connected to the plurality of sheet patterns, a power rail which is on a second side of the first substrate, a via pattern which extends through the first substrate in the first direction, and is connected to both the power rail and the source/drain pattern, a first dummy pattern on the via pattern, a second substrate on the first dummy pattern, and a second dummy pattern on a third side of the second substrate that faces the first side of the first substrate.

A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.