A method for fabricating a transistor can include forming a plurality of source regions and a plurality of drain regions arranged in an alternating manner, such that each of the source regions and the drain regions is implemented as a first type active region; and implementing a plurality of gate structures relative to the source regions and the drain regions such that application of a voltage to each gate structure results in formation of a conductive channel between a respective pair of source and drain regions. The method can further include forming a body region to provide the respective conductive channel upon the application of the voltage to the corresponding gate structure, such that the body region is implemented as a second type active region; and forming a recessed region at an end of each drain region and one or both of the gate structures adjacent to the drain region.

A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.

Transistor designs for floating body memory, and associated devices and systems, are disclosed. In one aspect, a transistor of a floating body memory cell includes a layer of a first semiconductor material between a first S/D contact and a first S/D region of the transistor, and a layer of a second semiconductor material between a second S/D contact and a second S/D region of the transistor, where the first and second semiconductor materials differ in at least one of a thickness, a bandgap, or a doping concentration.

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.

A 3D semiconductor device, including: a first level including a first single crystal layer, memory control circuits, and first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer connected to the first metal layer, at least one Phase-Lock-Loop or Digital-Lock-Loop circuit; a second level overlaying the first level including second transistors, a third level overlaying the second level and including third transistors; a fourth level overlaying the third level and including fourth transistors, the second level includes first memory cells, where each includes at least one of the second transistors which may include a metal gate, the fourth level includes second memory cells which each includes at least one of the fourth transistors, where the memory control circuits control writing to the second memory cells, where at least one of the second transistors includes a hafnium-oxide gate dielectric.

Si bodies 24aa to 24ad, 24ba to 24bd, and 45a to 45d are disposed parallel to a substrate 20 and are adjacent to each other in a horizontal direction at regular intervals. A HfO.sub.2 layer 27b surrounds the Si bodies 24aa to 45d. TiN layers 34a to 34d surround the HfO.sub.2 layer 27b, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodies 45a to 45d are formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layers 52a to 52d are connected to the TiN layers 34a to 34d and extend up to above an insulating layer 50 through contact holes 51a to 51d extending in a vertical direction from the terminating ends of the TiN layers 34a to 34d. The metal wiring layers 52a to 52d are connected to word lines WL1 to WL4.

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the single crystal first transistors or the second transistors include at least two FinFet transistors, and where two of the at least two FinFet transistors have different threshold voltages (Vt).

Novel NEDMOS and/or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a Vbi Reduction Material (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.