A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Methods to fabricate a semiconductor device, the method including: forming a first level, the first level including a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers, where each transistor of the plurality of transistors includes a single crystal channel, and where the plurality of first metal layers include interconnections between the transistors of the plurality of transistors; thinning the single crystal silicon layer to a thickness of less than two microns; forming a second level, the second level including a plurality of second metal layers, where the second level is disposed underneath the first level; and forming a connection path between at least one of the transistors to at least one of the plurality of second metal layers, where the connective path includes at least one via disposed through at least the single crystal silicon layer.

A multi-time programable (MTP) memory cell is described. The MTP memory cell includes a buried oxide (BOX) layer. The MTP memory cell also includes a semiconductor-on-insulator (SOI) layer on the BOX layer. The MTP memory cell further includes a planar multi-gate structure. The planar multi-gate structure includes a pass-gate on the SOI layer. The planar multi-gate structure also includes a memory-gate.

By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (FeFETs), thereby providing a very high-speed, high-density memory array.

The present disclosure relates to semiconductor structures and, more particularly, to memory devices and methods of manufacture. The structure includes: a gate structure having a gate dielectric material and a gate body; a body region under the gate dielectric material; a first doped region laterally adjacent to a first side of the body region; a second doped region laterally adjacent to the first doped region; and a shallow trench isolation structure laterally adjacent to a second side of the body region.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

The present disclosure generally relates to semi-floating junction isolation. In an example, a semiconductor device includes an epitaxial layer, a buried layer, a deep well, a drift well, a contact well, and a contact region. The buried layer, deep well, drift well, contact well, and contact region each have a conductivity type opposite from a conductivity type of the epitaxial layer. The buried layer is spaced apart from a top surface of the epitaxial layer. The deep well extends in the epitaxial layer and touches the buried layer. The deep well laterally encircles an active area over the buried layer. The drift well extends in the epitaxial layer to a depth and extends laterally from the deep well towards the active area. The contact well extends in the epitaxial layer to a greater depth and touching the drift well. The contact region extends in the contact well.

Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.

Disclosed structures and methods include a chip including a transistor between an insulator layer and dielectric material layers. The transistor includes: within an active device region, source and drain regions and stacked body and channel regions laterally between the source and drain regions; and a gate structure on a surface of the active device region adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: within an active device region, a source region laterally between drain and stacked body and channel regions laterally between the source region and each drain region; and gate structures on a surface of the active device region adjacent to and between the channel regions, respectively, and the dielectric material layers. In any case, a local interconnect adjacent to another surface of the active device region opposite the gate structure(s) electrically couples the body region to the source region(s).