Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.

Semiconductor devices with switchable connection between body and a ground node are presented. Methods for operating and fabricating such semiconductor devices are also presented.

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. The floating body region is surrounded on all sides by gate region and may include a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET. The floating body region is configured to have at least first and second stable states.

3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.

A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions, and trap source atoms within the stacked groups of layers. Each memory call may also include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Trap source atoms may also be within the stacked groups of layers. Each memory cell may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.