A method of forming a patterned metal film layer and preparation methods of a transistor and an array substrate are disclosed, in the technical field of displays. The method of forming a patterned metal film layer of the invention comprises: sequentially depositing a sacrificial layer and a photoresist layer on a substrate, and forming a patterned sacrificial layer and a patterned photoresist layer overlying on the patterned sacrificial layer by exposure, development, and etching, wherein a side wall of the patterned sacrificial layer adjacent to a patterned metal film layer to be formed forms a chamfer; depositing a metal film layer on the substrate after finishing the above step, and removing the patterned photoresist layer and the sacrificial layer to form a patterned metal film layer.

An array substrate and a manufacturing method thereof, a display panel, and a display device are provided. The array substrate includes a substrate; a source-drain metallic layer and a first passivation metallic protective layer formed in sequence on the substrate, the source-drain metallic layer including a source electrode and a drain electrode not contacted with each other; a conductive protection layer formed on the substrate on which the first passivation metallic protection layer has been formed; and a pixel electrode formed on the substrate on which the conductive protection layer has been formed, the pixel electrode contacting the conductive protection layer.

Electric charge is stored, in accordance with a bias voltage, in a gate of a transistor performing switching operation between an input terminal and an output terminal, and the gate is brought into an electrically floating state at the time of completing the storage of electric charge in the gate. One electrode of a capacitor is connected to the gate in an electrically floating state, and the potential of the other electrode of the capacitor is increased, so that the voltage of the gate is increased using capacitive coupling. The potential of the gate of the transistor is increased, and the bias voltage is sampled without being decreased. Each of the transistor performing switching operation and a transistor connected to the gate of the transistor is a transistor with an extremely low off-state current.

A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.

A display panel is provided. The display panel has an active area and a border area out of the active area. The display panel includes a plurality of pixels, a first gate driver portion, a plurality of scan lines and a multiplexer portion. The pixels are located in the active area. The first gate driver portion is located in the border area. The scan lines are located in the active area, and connected to the first gate driver portion. The multiplexer portion is located in the border area. The multiplexer portion and the first gate driver portion at least partially overlap along a direction parallel to one of the plurality of scan lines.

An array substrate, a display apparatus applying the same and the assembly method thereof are provided, wherein the array substrate includes a substrate having a plurality of pixels, each of the pixels at least includes a thin film transistor (TFT) device, a first electrode, a second electrode separated from the first electrode all of which are disposed on the substrate. at least one of the first electrode and the second electrode is electrically contacted to the TFT device, and either the first electrode or the second electrode has a magnetic force generator used to generate a magnetic force substantially ranging from 10 gauss to 1000 gauss.

A TN-type array substrate and a fabrication method thereof, and a display device, the fabrication method of the TN-type array substrate includes: a step of forming a first metal layer, a gate insulating layer, an active layer, a second metal layer and a transparent conductive layer on a substrate, wherein the first metal layer includes a gate electrode, the second metal layer includes a data line, the transparent conductive layer includes a pixel electrode; and wherein the forming the second metal layer and the transparent conductive layer includes: sequentially forming a transparent conductive thin film and a metal thin film on the substrate; performing one-off patterning process on the transparent conductive thin film and the metal thin film to form a thin film transistor (TFT) channel region, the transparent conductive layer and the second metal layer.

An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. A patternized third metal layer is between the bottom transparent conductive layer and the protective layer and includes a first zone and a second zone intersecting the first zone. The first zone shields the source line. A portion of the second zone overlaps a side portion of the light shield layer that is close to the source/drain electrode.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor layer, a gate electrode on the semiconductor layer, a first insulating layer between the semiconductor layer and the gate electrode; a second insulating layer on the gate electrode, source and drain electrodes corresponding to both ends of the semiconductor layer and disposed on the second insulating layer, and a doping layer disposed along contact holes of the first and second insulating layers, which expose the both ends of the semiconductor layer, such as, between the both ends of the semiconductor layer and the source and drain electrodes.

A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.