A transparent conductive film includes a metal chalcogenide compound doped with a halogen and having a sheet resistance at room temperature of less than or equal to about 60 ohm/sq.

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.

The disclosure provides a thin-film transistor, a manufacturing method thereof, an array substrate and a display panel, and belongs to the technical field of thin-film transistor devices. The thin-film transistor includes a base substrate, an active layer on the base substrate including a plurality of semiconductor nanowires, and a plurality of guiding projections on the base substrate which extend along a first direction and are arranged at intervals and each of which includes two side walls extending along the first direction, and the semiconductor nanowire extends along a side wall of the guiding projection. In the thin-film transistor, since the semiconductor nanowires are used as the active layer, mobility and concentration of carriers in the thin-film transistor can be effectively increased and therefore performance of the thin-film transistor can be improved. A length of the semiconductor nanowire is not limited, and a size of the thin-film transistor is not limited.

A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.