A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.

A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose.

A method for manufacturing a semiconductor device includes forming a doped silicon layer on a bulk substrate, forming an undoped silicon cap layer on the doped silicon layer, forming a stacked configuration of silicon germanium (SiGe) and silicon layers on the undoped silicon cap layer, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on an SiGe layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, the doped silicon layer and the undoped silicon cap layer, forming a spacer layer on each of the plurality of dummy gates, and on the doped silicon layer and the undoped silicon cap layer, selectively etching the doped silicon layer with respect to the undoped silicon layer, and filling the area from where the doped s silicon layer was selectively removed with a dielectric layer.

Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

A semiconductor device capable of maintaining data even after instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors. The first and fourth transistors are p-channel transistors. The second and fifth transistors are n-channel transistors. In the third and sixth transistors, a channel formation region is included in an oxide semiconductor layer. A high voltage is applied to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor. A low voltage is applied to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor.

A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.