Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie.

An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor comprises: a gate electrode (11), a source electrode (15) and a drain electrode (16), and the thin film transistor further comprises a buffer layer (11) which is directly provided at one side or both sides of at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16), wherein, the buffer layer (11) and at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16) directly contacting the buffer layer (11) are conformal. Therefore, the adhesion between an electrode of the thin film transistor and a film layer contacting it is improved and at the same time an atom in the electrode of the thin film transistor is effectively prevented from diffusing to the film layer connected with it, and the reliability of the thin film transistor is improved and the production cost is reduced.

Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

A thin film transistor (TFT) includes a semiconductive layer, a first inter-layer drain (ILD) layer, a second ILD layer, and at least one contact hole passing through the first ILD layer and the second ILD layer. The semiconductive layer includes a channel region, a first lightly doped drain (LDD) region, a second LDD region, a first heavily doped drain (HDD) region, and a second HDD region. The at least one contact hole includes a first portion passing through the second ILD layer and a second portion passing through the first ILD layer. The second portion gradually narrows along a direction from a top to a bottom of the first ILD layer.

A method of manufacturing a thin film transistor substrate includes forming an amorphous silicon layer on a substrate, the substrate having a rectangular shape, and irradiating the amorphous silicon layer with a laser beam at a random pitch, such that the amorphous silicon layer is crystallizes into a polycrystalline silicon layer, wherein the laser beam has a major axis and a minor axis, the major axis being non-parallel with respect to sides of the substrate.

A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.