A display device is provided. The display device includes a first substrate; a first transistor and a second transistor disposed over the first substrate; a common electrode disposed over the first substrate; and a light-emitting diode chip (LED chip) disposed over the first substrate and disposed corresponding to the first transistor and the second transistor. The light-emitting diode chip includes a first light-emitting unit and a second light-emitting unit, wherein the first light-emitting unit is electrically connected to the first transistor and the common electrode, and the second light-emitting unit is electrically connected to the second transistor and the common electrode.

A display device includes overlapping two display panels. The display panel on the upper side includes a first display region and a region that transmits visible light. The display panel on the lower side includes a second display region and a region that blocks visible light. The second display region overlaps with the region that transmits visible light. The region that blocks visible light overlaps with the first display region. The display panel on the lower side includes a third display region between the second display region and the region that blocks visible light. The gate signal and the source signal supplied to a first pixel in the third display region are the same as the gate signal and the source signal supplied to a second pixel in the second display region. The second pixel is closer to the first pixel than any other pixels included in the second display region.

A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

A semiconductor device includes a series of layers formed on a substrate, including a first plurality of n-type layers, a second plurality of layers that form a p-type modulation doped quantum well structure (MDQWS), a third plurality of layers disposed between the p-type MDQWS and a fourth plurality of layers that form an n-type MDQWS, and a fifth plurality of p-type layers. The first plurality of layers includes a first etch stop layer of n-type formed on an n-type contact layer. The third plurality of layers includes a second etch stop layer formed above the p-type MDQWS and a third etch stop layer formed above and offset from the second etch stop layer. The fifth plurality of layers includes a fourth etch stop layer of p-type formed above the n-type MDQWS and a fifth etch stop layer of p-type doping formed above and offset from the fourth etch stop layer.

A semiconductor device includes: a silicon layer having a thickness in a range of 2 m to 200 m between a frontside and a backside of the silicon layer; a first device region and a second device region laterally isolated from one another in the silicon layer by an isolation structure that extends from the frontside to the backside of the silicon layer; a first insulation layer on the frontside of the silicon layer; a first patterned metallization on the first insulation layer; a second insulation layer on the backside of the silicon layer; and a second patterned metallization on the second insulation layer. The first patterned metallization provides lateral electrical routing along the frontside of the silicon layer. The second patterned metallization provides lateral electrical routing along the backside of the silicon layer. Additional embodiments of semiconductor devices and methods of producing the semiconductor devices are also described.

A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

Various embodiments of solid state transducer (SST) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer is bonded to an LED wafer and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. A single dielectric layer in a panel may encapsulate all the RGB modules to form a compact and inexpensive panel. Various addressing techniques are described for both a color display and a lighting panel. Various circuits are described for reducing the sensitivity of the LED to variations in input voltage.

A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.

An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.