A thin film transistor and a preparation method therefor, an array substrate and a display apparatus. The thin film transistor comprises an active layer (4), an etched barrier layer (5) disposed on the active layer (4), and a source and drain (6) disposed on the etched barrier layer (5). The source and drain (6) are disposed on a same layer in a spaced manner. First via holes (7) are formed in the etched barrier layer (5), second via holes (8) are formed in positions in the active layer (4) corresponding to the first via holes (7). The source and drain (6) are connected to the active layer (4) through the first via holes (7) formed in the etched barrier layer (5) and the second via holes (8) formed in the active layer (4). Because two second via holes are formed in the active layer, a design value L1 of the channel region length of the active layer is shortened and a metal oxide semiconductor array substrate with a narrow channel is formed and the charge rate is high, which helps to improve the display effect.

A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials.

A complementary transistor pair with an n-type enhancement-mode field effect transistor and a p-type field effect transistor is disclosed. The n-type enhancement-mode field effect transistor uses a metal oxide channel layer having a material selected from SnO.sub.2, ITO, ZnO, SnO.sub.2 and In.sub.2O.sub.3 while the p-type field effect transistor uses a germanium-containing channel layer.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.

A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.

An image sensor is provided which is capable of holding data for one frame period or longer and conducting a difference operation with a small number of elements. A photosensor is provided in each of a plurality of pixels arranged in a matrix, each pixel accumulates electric charge in a data holding portion for one frame period or longer, and an output of the photosensor changes in accordance with the electric charge accumulated in the data holding portion. As a writing switch element for the data holding portion, a transistor with small leakage current (sufficiently smaller than 110.sup.14 A) is used. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer.

Provided are an oxide sintered compact whereby low carrier density and high carrier mobility are obtained when the oxide sintered compact is used to obtain an oxide semiconductor thin film by a sputtering method, and a sputtering target which uses the oxide sintered compact. This oxide sintered compact contains, as an oxide, one or more positive divalent elements selected from the group consisting of indium, gallium, nickel, cobalt, calcium, strontium, and lead. The gallium content is less than 0.08 to 0.20 in terms of Ga/(In+Ga) atomic ratio, and the positive dyad (M) content is 0.0001 to 0.05 in terms of M/(In+Ga+M) atomic ratio. In a crystalline oxide semiconductor thin film formed using the oxide sintered compact as a sputtering target, the carrier density is less than 110.sup.18 cm.sup.3, and the carrier mobility is at least 10 cm.sup.2V.sup.1sec.sup.1.

Provided is an oxide sintered body that, when used to obtain an oxide semiconductor thin film by sputtering, can achieve a low carrier concentration and a high carrier mobility. Also provided is a sputtering target using the oxide sintered body. The oxide sintered body contains, as oxides, indium, gallium, and at least one positive divalent element selected from the group consisting of nickel, cobalt, calcium, strontium, and lead. The gallium content, in terms of the atomic ratio Ga/(In+Ga), is from 0.20 to 0.45, and the positive divalent element content, in terms of the atomic ratio M/(In+Ga+M), is from 0.0001 to 0.05. The amorphous oxide semiconductor thin film, which is formed using the oxide sintered body as a sputtering target, can achieve a carrier concentration of less than 3.010.sup.18 cm.sup.3 and a carrier mobility of at least 10 cm.sup.2V.sup.1 sec.sup.1.

The present disclosure is to provide an optoelectronic device. The optoelectronic device comprises a heat dispersion substrate; an insulative protection layer on the heat dispersion substrate, wherein the insulative protection layer comprises AlInGaN series material; and an optoelectronic unit comprising an epitaxial structure comprising multiple layers on the insulative protection layer, wherein at least one layer of the epitaxial structure comprises III-V group material devoid of nitride.

A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer.