The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.

The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor element and an electronic device each including the oxide semiconductor layer. The invention provides an exemplary method of producing an oxide semiconductor layer, and the method includes the precursor layer forming step of forming, on or above a substrate, a layered oxide semiconductor precursor including a compound of metal to be oxidized into an oxide semiconductor dispersed in a solution including a binder made of aliphatic polycarbonate, and the annealing step of heating the precursor layer at a first temperature achieving decomposition of 90 wt % or more of the binder, and then annealing the precursor layer at a temperature equal to or higher than a second temperature (denoted by X) that is higher than the first temperature, achieves bonding between the metal and oxygen, and has an exothermic peak value in differential thermal analysis (DTA).

The present invention generally relates to nanoscale wires, and to systems and methods of producing nanoscale wires. In some aspects, the present invention is generally related to facet-specific deposition on semiconductor surfaces. In one embodiment, a first surface of a nanoscale wire, or a semiconductor, is preferentially oxidized relative to a second surface, and material is preferentially deposited on the second surface relative to the first surface. For example, the nanoscale wire or semiconductor may be a silicon nanowire that is initially exposed to an etchant to remove silicon oxide, then exposed to an oxidant under conditions such that one facet or surface (e.g., a {113} facet) is oxidized more quickly than another facet or surface (e.g., a {111} facet). Material may then be deposited or immobilized on the less-oxidized facet relative to the more-oxidized facet. Other embodiments of the invention may be directed to articles made thereby, devices containing such nanoscale wires or semiconductors, kits involving such nanoscale wires or semiconductors, semiconductor surfaces, or the like.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 cm.sup.2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

Two-dimensional (2D) transition-metal dichalcogenides have emerged as a promising material system for optoelectronic applications, but their primary figure-of-merit, the room-temperature photoluminescence quantum yield (QY) is extremely poor. The prototypical 2D material, MoS.sub.2 is reported to have a maximum QY of 0.6% which indicates a considerable defect density. We report on an air-stable solution-based chemical treatment by an organic superacid which uniformly enhances the photoluminescence and minority carrier lifetime of MoS.sub.2 monolayers by over two orders of magnitude. The treatment eliminates defect-mediated non-radiative recombination, thus resulting in a final QY of over 95% with a longest observed lifetime of 10.80.6 nanoseconds. Obtaining perfect optoelectronic monolayers opens the door for highly efficient light emitting diodes, lasers, and solar cells based on 2D materials.

A method of manufacturing ZnO-containing semiconductor structure includes steps of: (a) forming a subsidiary lamination, including alternately laminating at least two periods of active oxygen layers and ZnO-containing semiconductor layers doped with at least one species of group 3B element; (b) alternately laminating said subsidiary lamination and AgO layer, sandwiching an active oxygen layer, to form lamination structure; and (c) carrying out annealing in atmosphere in which active oxygen exists and pressure is below 10.sup.2 Pa, intermittently irradiating oxygen radical beam on a surface of said lamination structure, forming a p-type ZnO-containing semiconductor structure co-doped with said group 3B element and Ag.

An enhancement-depletion circuit element includes a depletion-mode load transistor and an enhancement-mode drive transistor formed from the common elements of: a first patterned conductive layer including a load gate electrode and a drive gate electrode; a patterned inorganic dielectric stack including a load gate dielectric and a drive gate dielectric; a patterned inorganic semiconductor layer including a load semiconductor region and a drive semiconductor region; a second patterned conductive layer including a load source, a load drain, a drive source and a drive drain; and a patterned differential passivation structure having a patterned polymer dielectric layer and a patterned conformal inorganic dielectric layer. The depletion-mode load transistor has a load back-channel in contact with the patterned conformal inorganic dielectric layer. The enhancement-mode drive transistor has a drive back-channel in contact with the patterned polymer dielectric layer.

Transition metal dichalcogenide (TMD)-based spintronics devices, each including a TMD thin film layer, a first gate electrode, a first insulating layer sandwiched between the TMD thin film layer and the first gate electrode, a second gate electrode, and a second insulating layer sandwiched between the TMD thin film layer and the second gate electrode. Such a device, when also including a source electrode and a drain electrode, functions as a spin filter. On the other hand, when also including one source electrode and two drain electrode terminals, such a device functions as a spin separator. Also disclosed are methods of using the above-described TMD-based spintronics devices.