H10D62/86

Field-effect transistor and semiconductor device
09613961 · 2017-04-04 · ·

According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.

METHOD OF CONTROLLING ELECTRIC CONDUCTIVITY OF METAL OXIDE THIN FILM AND THIN FILM TRANSISTOR INCLUDING THE METAL OXIDE FILM HAVING THE CONTROLLED ELECTRIC CONDUCTIVITY

A method for controlling an electric conductivity of a metal oxide thin film is disclosed. The method may include forming a metal oxide thin film; applying thermal treatment to the metal oxide thin film; and irradiating UV (ultraviolet)-rays to the metal oxide thin film in an atmosphere containing water molecules and oxygen molecules. Thus, the hydrogen may be doped into the metal oxide thin film to improve the electric conductivity of the metal oxide thin film.

HEMT HAVING HEAVILY DOPED N-TYPE REGIONS AND PROCESS OF FORMING THE SAME
20170092747 · 2017-03-30 ·

A HEMT made of nitride semiconductor materials and a process of forming the same are disclosed, where the HEMT has n-type regions beneath the source and drain electrodes with remarkably increased carrier concentration. The HEMT provides the n-type regions made of at least one of epitaxially grown ZnO layer and MgZnO layer each doped with at least aluminum and gallium with density higher than 110.sup.20 cm.sup.3. The process of forming the HEMT includes steps of forming recesses by dry-etching, epitaxially growing n-type layer, removing surplus n-type layer except within the recesses by dry-etching using hydrocarbon, and forming the electrodes on the n-type layer.

Dual active layer semiconductor device and method of manufacturing the same

Some embodiments include a semiconductor device. The semiconductor device includes a transistor having a gate metal layer, a transistor composite active layer, and one or more contact elements over the transistor composite active layer. The transistor composite active layer includes a first active layer and a second active layer, the first active layer is over the gate metal layer, and the second active layer is over the first active layer. Meanwhile, the semiconductor device also includes one or more semiconductor elements forming a diode over the transistor. The semiconductor element(s) have an N-type layer over the transistor, an I layer over the N-type layer, and a P-type layer over the I layer. Other embodiments of related systems and methods are also disclosed.

CONTROLLED GROWTH OF NANOSCALE WIRES

The present invention generally relates to nanoscale wires, and to methods of producing nanoscale wires. In some aspects, the nanoscale wires are nanowires comprising a core which is continuous and a shell which may be continuous or discontinuous, and/or may have regions having different cross-sectional areas. In some embodiments, the shell regions are produced by passing the shell material (or a precursor thereof) over a core nanoscale wire under conditions in which Plateau-Raleigh crystal growth occurs, which can lead to non-homogenous deposition of the shell material on different regions of the core. The core and the shell each independently may comprise semiconductors, and/or non-semiconductor materials such as semiconductor oxides, metals, polymers, or the like. Other embodiments are generally directed to systems and methods of making or using such nanoscale wires, devices containing such nanoscale wires, or the like.

DUAL-MATERIAL MANDREL FOR EPITAXIAL CRYSTAL GROWTH ON SILICON
20170077146 · 2017-03-16 ·

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.

Two-dimensional (2D) material element with in-plane metal chalcogenide-based heterojunctions and devices including said element

According to example embodiments, a two-dimensional (2D) material element may include a first 2D material and a second 2D material chemically bonded to each other. The first 2D material may include a first metal chalcogenide-based material. The second 2D material may include a second metal chalcogenide-based material. The second 2D material may be bonded to a side of the first 2D material. The 2D material element may have a PN junction structure. The 2D material element may include a plurality of 2D materials with different band gaps.

Method for preparing nanostructure by electrochemical deposition, and nanostructure prepared thereby

The present invention relates to a method for preparing a nanostructure by electrochemical deposition, and a nanostructure prepared thereby, and more specifically, to: a method for preparing a nanostructure by electrochemical deposition, wherein it is possible to prepare a nanostructure having remarkable morphological, structural and optical characteristics by controlling a method for applied power during electrochemical deposition; and a nanostructure prepared thereby.

OXIDE SINTERED BODY AND METHOD FOR MANUFACTURING THE SAME, SPUTTERING TARGET, AND SEMICONDUCTOR DEVICE
20170069474 · 2017-03-09 ·

There is provided an oxide sintered body including indium, tungsten and zinc, wherein the oxide sintered body includes a bixbite type crystal phase as a main component and has an apparent density of higher than 6.6 g/cm.sup.3 and equal to or lower than 7.5 g/cm.sup.3, a content rate of tungsten to a total of indium, tungsten and zinc in the oxide sintered body is higher than 0.5 atomic % and equal to or lower than 5.0 atomic %, a content rate of zinc to the total of indium, tungsten and zinc in the oxide sintered body is equal to or higher than 1.2 atomic % and equal to or lower than 19 atomic %, and an atomic ratio of zinc to tungsten is higher than 1.0 and lower than 60. There are also provided a sputtering target including this oxide sintered body, and a semiconductor device.

Crystalline multilayer structure and semiconductor device
09590050 · 2017-03-07 · ·

Provided is a crystalline multilayer structure having good semiconductor properties. In particular, the crystalline multilayer structure has good electrical properties as follows: the controllability of conductivity is good; and vertical conduction is possible. A crystalline multilayer structure includes a metal layer containing a uniaxially oriented metal as a major component and a semiconductor layer disposed directly on the metal layer or with another layer therebetween and containing a crystalline oxide semiconductor as a major component. The crystalline oxide semiconductor contains one or more metals selected from gallium, indium, and aluminum and is uniaxially oriented.