In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.

The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor element and an electronic device each including the oxide semiconductor layer. The invention provides an exemplary method of producing an oxide semiconductor layer, and the method includes the precursor layer forming step of forming, on or above a substrate, a layered oxide semiconductor precursor including a compound of metal to be oxidized into an oxide semiconductor dispersed in a solution including a binder made of aliphatic polycarbonate, and the annealing step of heating the precursor layer at a first temperature achieving decomposition of 90 wt % or more of the binder, and then annealing the precursor layer at a temperature equal to or higher than a second temperature (denoted by X) that is higher than the first temperature, achieves bonding between the metal and oxygen, and has an exothermic peak value in differential thermal analysis (DTA).

Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.

A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core.

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

A semiconductor device that includes a first conductor (233a1), a second conductor (231), a first transistor (201) over a first insulator, and a second insulator (282) over the first insulator is provided. The first transistor includes a third conductor (242a) and a fourth conductor (242b) that are each electrically connected to a first metal oxide (230), a third insulator (253, 254) over the first metal oxide, and a fifth conductor (260) over the third insulator. The fourth conductor includes a second layer over a first layer. The top surface of the fifth conductor includes a region in contact with the second insulator. The first conductor includes a portion positioned inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion positioned inside an opening of the second insulator. The second conductor includes a region in contact with the second layer and a portion positioned inside an opening of the second insulator. The top surface of the first conductor and the top surface of the second conductor are level with each other.

A semiconductor device that includes a first conductor (233a1), a second conductor (231), a first transistor (201) over a first insulator, and a second insulator (282) over the first insulator is provided. The first transistor includes a third conductor (242a) and a fourth conductor (242b) that are each electrically connected to a first metal oxide (230), a third insulator (253, 254) over the first metal oxide, and a fifth conductor (260) over the third insulator. The fourth conductor includes a second layer over a first layer. The top surface of the fifth conductor includes a region in contact with the second insulator. The first conductor includes a portion positioned inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion positioned inside an opening of the second insulator. The second conductor includes a region in contact with the second layer and a portion positioned inside an opening of the second insulator. The top surface of the first conductor and the top surface of the second conductor are level with each other.

Provided is a semiconductor device. The semiconductor device includes a first electrode, a second electrode spaced apart from the first electrode, a channel between the first electrode and the second electrode, a gate insulating layer in the channel, and a gate electrode on the gate insulating layer. The channel includes a plurality of oxide semiconductor layers spaced apart from each other and a crystallization reduction layer between the plurality of oxide semiconductor layers.

Provided is a semiconductor device. The semiconductor device includes a first electrode, a second electrode spaced apart from the first electrode, a channel between the first electrode and the second electrode, a gate insulating layer in the channel, and a gate electrode on the gate insulating layer. The channel includes a plurality of oxide semiconductor layers spaced apart from each other and a crystallization reduction layer between the plurality of oxide semiconductor layers.

Addressable actuator and arrays thereof are described. Actuators may be dielectric elastomer actuators (DBAs). An addressable actuator may include a compliant substrate, with an optical receiver integrated with a first region of the compliant substrate and an actuator integrated with a second region of the compliant substrate, with the optical receiver coupled to the actuator. The optical receivers may comprise percolating networks of semiconductor materials, such as photoconductive channels of zinc oxide nanowires, which may be embedded in a compliant substate, or one or more compliant layers (which may be formed on a substrate). Compliant substrates or layers may include complaint materials such as an elastomer. An actuator array may comprise multiple of the actuators, with each actuator being independently optically addressable. A system may include light emitting devices optically coupled to respective optical receivers to control actuation of the actuators using light.