An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500 C. and 550 C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.

Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

A method for manufacturing a solar cell can include a tunnel layer forming step of forming a tunnel layer on a first surface of a semiconductor substrate, a first conductive type semiconductor region forming step of forming a first conductive type semiconductor region on the first surface of the semiconductor substrate, a second conductive type semiconductor region forming step of forming a second conductive type semiconductor region by doping impurities of a second conductive type into a second surface of the semiconductor substrate, a first passivation film forming step of forming a first passivation film on the first conductive type semiconductor region and an electrode forming step of forming a first electrode connected to the first conductive type semiconductor region and a second electrode connected to the second conductive type semiconductor region.

Reduction of solar wafer LID by exposure to continuous or intermittent High-Intensity full-spectrum Light Radiation, HILR, by an Enhanced Light Source, ELS, producing 3-10 Sols, optionally in the presence of forming gas or/and heating to within the range of from 100 C.-300 C. HILR is provided by ELS modules for stand-alone bulk/continuous processing, or integrated in wafer processing lines in a High-Intensity Light Zone, HILZ, downstream of a wafer firing furnace. A finger drive wafer transport provides continuous shadowless processing speeds of 200-400 inches/minute in the integrated furnace/HILZ. Wafer dwell time in the peak-firing zone is 1-2 seconds. Wafers are immediately cooled from peak firing temperature of 850 C.-1050 C. in a quench zone ahead of the HILZ-ELS modules. Dwell in the HILZ is from about 10 sec to 5 minutes, preferably 10-180 seconds. Intermittent HILR exposure is produced by electronic control, a mask, rotating slotted plate or moving belt.

A photovoltaic device includes a substrate structure and a p-type semiconductor absorber layer, the substrate structure including a CdSSe layer. A photovoltaic device may alternatively include a CdSeTe layer. A process for manufacturing a photovoltaic device includes forming a CdSSe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming a p-type absorber layer above the CdSSe layer.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

One embodiment of the present invention can provide a system for fabrication of a photovoltaic structure. The system can include a physical vapor deposition tool configured to sequentially deposit a transparent conductive oxide layer and a metallic layer on an emitter layer formed in a first surface of a Si substrate, without requiring the Si substrate to be removed from the physical vapor deposition tool after depositing the transparent conductive oxide layer. The system can further include an electroplating tool configured to plate a metallic grid on the metallic layer and a thermal annealing tool configured to anneal the transparent conductive oxide layer.

The precursor comprises at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material. The method comprises the steps of placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer, then applying a state change electrical voltage (U1) between the conducting layer and ground, the said state change electrical voltage (U1) being designed to bring the Fermi level at the interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the said amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature (T.sub.E), and finally cooling down the cell precursor (10) prior to interrupting the application of the state change electrical voltage (U1).

A method of preparing Group XIII selenide nanoparticles comprises reacting a Group XIII ion source with a selenol compound. The nanoparticles have an M.sub.xSe.sub.y Semiconductor core (where M is In or Ga) and an organic capping ligand attached to the core via a carbon-selenium bond. The selenol provides a source of selenium for incorporation into the semiconductor core and also provides the organic capping ligand. The nanoparticles are particularly suitable for solution-based methods of preparing semiconductor films.