A semiconductor device includes a main element and a sensing element each including a drift region of a first conductivity-type, a well region of a second conductivity-type provided at an upper part of the drift region, a first main electrode region of the first conductivity-type provided at an upper part of the well region, a gate electrode buried with a gate insulating film interposed in a trench, and a main electrode connected to the first main electrode region, the isolation region including an element-isolation insulating film provided on a top surface of a semiconductor base body interposed between the well regions, and a first wire provided on a top surface of the element-isolation insulating film and electrically connected to the main electrode of the main element.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

A semiconductor device includes a main element and a sensing element each including a drift region of a first conductivity-type, a well region of a second conductivity-type provided at an upper part of the drift region, a first main electrode region of the first conductivity-type provided at an upper part of the well region, a gate electrode buried with a gate insulating film interposed in a trench, and a main electrode connected to the first main electrode region, the isolation region including an element-isolation insulating film provided on a top surface of a semiconductor base body interposed between the well regions, and a first wire provided on a top surface of the element-isolation insulating film and electrically connected to the main electrode of the main element.

A silicon carbide semiconductor device has a cell region that includes a main cell region, a sense cell region, and an element isolation region electrically separating the main cell region and the sense cell region. The element isolation region includes a plurality of isolation trenches and a plurality of isolation deep layers of a second conductivity type. The isolation trenches are disposed between the main cell region and the sense cell region, and extend deeper than a base layer to separate the base layer into a section adjacent to the main cell region and a section adjacent to the sense cell region. The isolation deep layers are respectively disposed at bottom portions of the isolation trenches in contact with bottom surfaces of the isolation trenches.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

A power semiconductor device includes: a semiconductor substrate; a power transistor formed in a cell field of the semiconductor substrate; a reference terminal; a sense terminal; and a depletion mode sense transistor integrated in the semiconductor substrate and having a voltage tap region of a first conductivity type. The voltage tap region is electrically connected to the sense terminal and follows a drift zone potential of the power transistor until a normally conducting channel of the depletion mode sense transistor pinches off. A pinch-off point of the normally conducting channel of the depletion mode sense transistor is designed such that a voltage between the sense terminal and the reference terminal is clamped below a maximum drain/collector voltage of the power semiconductor device.