The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating parts. The third electrode includes first to third electrode regions. The third electrode region connects the first electrode region and the second electrode region. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes fifth and sixth insulating portions. A lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion.

A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, first and second insulating parts, and a connection part. The third electrode includes first to third electrode regions. The third electrode region connects the first electrode region and the second electrode region. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes fifth and sixth insulating portions. The connection part includes first and second connection parts. The first connection part is positioned between the third insulating region and the second insulating part. The second connection part is positioned between the third insulating region and the first connection part.

A semiconductor device, including: a semiconductor substrate containing silicon carbide, the semiconductor substrate having a first main surface and a second main surface opposite to each other; an n-type region provided in the semiconductor substrate; a p-type region provided in the semiconductor substrate, between the first main surface of the semiconductor substrate and n-type region, the p-type region being in contact with the n-type region; a first electrode electrically connected to the p-type region; and a second electrode electrically connected to the n-type region. At least one portion of the p-type region is a p-type polysilicon portion.

A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450 C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.

Provided is a semiconductor device, including a semiconductor substrate having an upper surface and a lower surface and including a bulk donor, wherein a hydrogen chemical concentration distribution of the semiconductor substrate in a depth direction is flat, monotonically increasing, or monotonically decreasing from the lower surface to the upper surface except for a portion where a local hydrogen concentration peak is provided; and a donor concentration of the semiconductor substrate is higher than a bulk donor concentration over an entire region from the upper surface to the lower surface. Hydrogen ions may be irradiated from the upper surface or the lower surface of the semiconductor substrate so as to penetrate the semiconductor substrate in the depth direction.

A power semiconductor device includes a substrate, a first epi layer of a first conductivity type disposed on the substrate, a second epi layer of a first conductivity type disposed on the first epi layer, a first well of a second conductivity type partially disposed in the first epi layer, a second well of a second conductivity type disposed on the second epi layer, an ion implantation region and a source region of the second conductivity type disposed in the second well, a source electrode in the source region, a gate insulating layer in a trench region where a portion of the ion implantation region and the second epi layer is removed, a trench gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the trench gate and a gate electrode electrically connected to the trench gate.

A semiconductor device according to an embodiment includes: first and second electrodes respectively provided on first and second main surfaces of a semiconductor layer; a first semiconductor region of a first conductivity type; a plurality of insulating regions formed to extend in a second direction orthogonal to a first direction from the second electrode toward the first electrode; a plurality of third electrodes provided in the plurality of insulating regions; a second semiconductor region of a second conductivity type sandwiched between the plurality of insulating regions, formed to extend in the second direction; a third semiconductor region of the first conductivity type located between the second semiconductor region and the first electrode; and a carrier conduction part formed to extend in the second direction in the second semiconductor region and electrically connected to the first electrode via a connection part not penetrating the third semiconductor region.

A method of manufacturing a lateral diffusion metal oxide semiconductor device. The method may include forming a high voltage deep N-well within a substrate, forming a high voltage N-well within the substrate, wherein the high voltage N-well is electrically coupled to the high voltage deep N-well, forming a drain terminal electrically coupled to the high voltage N-well, forming a source terminal, and forming a gate terminal disposed between the source terminal and the drain terminal. At least one of the high voltage N-well and the high voltage deep N-well may extend less than 2.0 microns beyond the drain terminal in a direction opposite from the source terminal.