A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.

A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a gate electrode (41), and a gate insulating layer (5). The semiconductor layer includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), and an n-type semiconductor region (14). The trench (3) is formed so as to penetrate through the p-type semiconductor layer (13) and to reach the second n-type semiconductor layer (12). The p-type semiconductor layer (13) includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench (3) is. Such structure allows suppressing dielectric breakdown in the gate insulating layer (5).

A resurf layer and a guard ring are formed in a peripheral region in a position at the surface of the semiconductor substrate. The guard ring is formed more deeply than the resurf layer. When the guard ring is shallow and the impurity concentration of the resurf layer is low, the potential distribution at the deep portion of the resurf layer becomes unstable, and the resurf layer does not sufficiently exhibit the effect of improving the withstand voltage. When the guard ring is deep, the impurity concentration of the guard ring is high, the potential distribution at the deep portion of the resurf layer is regulated by the guard ring and the resurf layer sufficiently exhibits the effect of improving the withstand voltage.

A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.

The present disclosure provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a well region and a drift region in the semiconductor substrate; and forming one or more counter-doped regions in the drift region, the one or more counter-doped regions being aligned along a direction vertical to the semiconductor substrate to divide the drift region into a plurality of parts. The semiconductor fabrication method also includes: forming a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and forming a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure.

A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n.sup.+-type emitter region, a p-type base region, and an n.sup.-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p.sup.+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n.sup.-type drift region, an emitter trench formed between the plurality of gate trenches adjacent to each other, and a buried electrode filled via an insulating film in the emitter trench, and electrically connected with the n.sup.+-type emitter region, and the emitter trench is disposed at an interval of 2 m or less via an n.sup.-type drift region with the gate trench.

A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor.

In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

The present invention is directed to III-V semiconductor trench MOSFETs comprising a buried field shield. The invention is further directed to an etch and regrowth method for forming this buried field shield. For example, in III-V trench MOSFETs with an n-type substrate, the region can be formed by an etch into the drift (n-type) and regrowth of p-type semiconductor to form the buried field shield in the trench area and a body/channel outside the trench area. With a narrow trench feature size, the regrowth will planarize enabling subsequent source epitaxy (n-type) without requiring ex-situ processing between body/channel and source growths, eliminating the need for additional masking of the regrowth.