Patent classifications
H10F39/026
Chip with automatic clock signal correction and automatic correction method
Disclosed are a chip with automatic clock signal correction and an automatic correction method. The chip includes a transmission interface, an oscillator and a correction logic circuit. The transmission interface provides a first clock signal. The oscillator generates a second clock signal. The correction logic circuit is coupled to the oscillator and the transmission interface, and performs correction operation to count the first clock signal to generate a first clock count value, and count the second clock signal to generate a second clock count value. When the first clock count value is equal to the first count target value, the correction logic circuit stops counting, and calculates a correction value based on the second clock count value and the second count target value. The correction logic circuit outputs the correction value to the oscillator, and the oscillator corrects a frequency of the second clock signal according to the correction value.
HETEROGENEOUS INTEGRATION USING WAFER-TO-WAFER STACKING WITH DIE SIZE ADJUSTMENT
A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.
IMAGE SENSORS AND METHODS OF FORMING THE SAME
An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.
INTEGRATED DEVICE FOR TEMPORAL BINNING OF RECEIVED PHOTONS
An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
To provide a semiconductor device which has transistor characteristics with little variation and includes an oxide semiconductor. The semiconductor device includes an insulating film over a conductive film and an oxide semiconductor film over the insulating film. The oxide semiconductor film includes a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer. The energy level of a bottom of a conduction band of the second oxide semiconductor layer is lower than those of the first and third oxide semiconductor layers. An end portion of the second oxide semiconductor layer is positioned on an inner side than an end portion of the first oxide semiconductor layer.
Dual Facing BSI Image Sensors with Wafer Level Stacking
A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
OPTICAL MODULES INCLUDING FOCAL LENGTH ADJUSTMENT AND FABRICATION OF THE OPTICAL MODULES
Fabricating optical devices can include mounting a plurality of singulated lens systems over a substrate, adjusting a thickness of the substrate below at least some of the lens systems to provide respective focal length corrections for the lens systems, and subsequently separating the substrate into a plurality of optical modules, each of which includes one of the lens systems mounted over a portion of the substrate. Adjusting a thickness of the substrate can include, for example, micro-machining the substrate to form respective holes below at least some of the lens systems or adding one or more layers below at least some of the lens systems so as to correct for variations in the focal lengths of the lens systems.
EDGE REFLECTION REDUCTION
An image sensor package includes an image sensor with a pixel array disposed in a semiconductor material. A first transparent shield is adhered to the semiconductor material, and the pixel array is disposed between the semiconductor material and the first transparent shield. The image sensor package further includes a second transparent shield, where the first transparent shield is disposed between the pixel array and the second transparent shield. A light blocking layer is disposed between the first transparent shield and the second transparent shield, and the light blocking layer is disposed to prevent light from reflecting off edges of the first transparent shield into the pixel array.
Method for forming deep trench spacing isolation for CMOS image sensors
A method for manufacturing an image sensor with deep trench spacing isolation is provided. A trench is formed in a semiconductor substrate, around and between a plurality of pixel regions of the semiconductor substrate. A cap is formed using epitaxy to seal a gap between sidewalls of the trench. Pixel sensors corresponding to the plurality of pixel regions are formed over or within the corresponding pixel regions. An image sensor resulting from the method is also provided.
AREA SENSOR AND DISPLAY APPARATUS PROVIDED WITH AN AREA SENSOR
An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.