Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

A brain-organoid complementary metal-oxide semiconductor (CMOS) processor and an associated method can be provided. For example, the CMOS structure can be a CMOS processor, which can be a co-processor. In addition or alternatively, the CMOS processor can include at least one culture which can comprise at least one brain organoid, and at least one CMOS device configured to interface with the at least one brain organoid. The CMOS device(s) can be configured to stimulate and record information from the brain organoid(s).

A semiconductor device includes: first fins (F-fins) and second fins (S-fin) arranged in a first row having a single-row height and that includes an alpha cell region and a beta cell region. The alpha cell region includes a first F-fin, a first S-fin and a first gate structure overlapping each of the first F-fin and the first S-fin. The first gate structure does not overlap top and bottom edges of the alpha cell region. The beta cell region includes second and third F-fins, second and third S-fins and a second gate structure overlapping each of the second F-fin and second S-fin and at least one of the third F-fin or the third S-fin. A top edge of the beta cell region being co-track aligned with the third F-fin. A bottom edge of the beta cell region being co-track aligned with the third S-fin.

An integrated circuit includes standard cells, first power lines extending in a first direction and providing a first power supply voltage to the standard cells, and second power lines extending in the first direction and providing a second power supply voltage to the standard cells, the first power lines and the second power lines being interleaved alternately in a second direction that is perpendicular to the first direction to define a rows between adjacent ones of the first and second power lines. The standard cells include first function cells arranged in first rows, extending in the first direction, and performing a first function using the first power supply voltage and the second power supply voltage, and other standard cells other than the first function cells are arranged in second rows among the rows.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

Provided is a method for manufacturing a power semiconductor device, which includes forming an active layer including a first active layer and a second active layer, which are doped with impurities different from each other, on an SiC substrate. The forming of the active layer includes preparing the SiC substrate comprising a first area and a second area, sequentially injecting a source gas mixed with a first doping gas, a purge gas, a reactant gas, and a purge gas onto the first area of the SiC substrate to form the first active layer, and sequentially injecting a source gas mixed with a second doping gas, a purge gas, a reactant gas, and a purge gas onto the second area of the SiC substrate to form the second active layer. The second doping gas and the first doping gas include elements different from each other, respectively. Thus, in accordance with exemplary embodiments, the active layer may be formed at a low temperature. Thus, the substrate or the thin film formed on the substrate may be prevented from being damaged by the high-temperature heat. In addition, the power or time required for heating the substrate to form the active layer may be saved, and the overall process time may be shortened. In addition, the active layer may be crystallized to be formed. That is, the crystallized active layer may be formed while forming the active layer at the low temperature.

In a semiconductor integrated circuit device, a plurality of cell rows each including standard cells arranged in the X direction are placed. The plurality of cell rows include a first cell row having a height H1 and a second cell row having a height H2 (H1<H2). The first cell row includes a logic cell and a cell having no logical function, and the second cell row includes a logic cell and a cell having no logical function. Nanosheets of the cells in the first cell row are smaller in width in the Y direction than nanosheets of the cells in the second cell row.

An IC package includes a transmitter and/or receiver positioned in a semiconductor die and including a signal terminal, a pad positioned on a first surface of the semiconductor die, the pad being electrically connected to the signal terminal, a passivation layer positioned on the first surface and including a first opening aligned with the pad, a first post-passivation interconnect (PPI) layer including a conductive path electrically connected to the pad, a second PPI layer including an antenna structure electrically connected to the conductive path, and a substrate positioned on a second surface of the semiconductor die opposite the passivation layer, the substrate including a plurality of through-substrate vias (TSVs) electrically coupled to the transmitter and/or receiver.

A layout structure of a standard cell lying astride standard cell rows different in height is provided. A double-height cell is formed astride first and second cell rows. The height of the second cell is greater than the height of the first cell. The double-height cell includes a first logic circuit that receives an input signal and outputs a signal to an internal node and a second logic circuit that receives the signal from the internal node and outputs an output signal. Transistors constituting the first logic circuit are formed in a region of the first cell row, and transistors constituting the second logic circuit are formed in a region of the second cell row.