In accordance with embodiments disclosed herein, there are provided methods and systems for implementing damage-and-resist-free laser patterning of dielectric films on textured silicon. For example, in one embodiment, such means include means for depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing; depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer; patterning the a-Si film to define an etch mask for the SiNx or SiOx layer; removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface; removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and plating the exposed c-Si surface with metal contacts. Other related embodiments are disclosed.

After forming an absorber layer containing cracks over a back contact layer, a passivation layer is formed over a top surface of the absorber layer and interior surfaces of the cracks. The passivation layer is deposited in a manner such that that the cracks in the absorber layer are fully passivated by the passivation layer. An emitter layer is then formed over the passivation layer to pinch off upper portions of the cracks, leaving voids in lower portions of the cracks.

A plurality of solar cell assembly series 9 of a solar cell panel are so arranged that any two adjacent solar cells in the plurality of solar cell assembly series 9 have a potential difference which does not exceed V volts which is a maximum output voltage of the plurality of solar cell assembly series 9. Electric discharges between any two adjacent solar cells can be prevented from occurring. Even when the output voltage of a solar cell module changes according to control by a power control circuit, electric discharges can be prevented from occurring between solar cell modules in the solar cell array in which any two adjacent solar cells in the plurality of solar cell assembly series 9 always have a potential difference which does not exceed V volts which is the maximum output voltage of the plurality of solar cell assembly series 9. In addition, the solar cell modules can be constructed of a combination of solar cell series patterns having line symmetry. In this case, while electric discharges can be prevented from occurring between any solar cells, the magnetic field caused by the solar cell circuitry can be reduced.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Disclosed are a solar cell and a method for manufacturing the same. A solar cell includes a semiconductor substrate, a tunnel layer on the first surface of the semiconductor substrate, a first conductive type semiconductor region on the tunnel layer and includes impurities of a first conductive type, a second conductive type semiconductor region on a second surface and includes impurities of a second conductive type opposite the first conductive type, a first passivation film on the first conductive type semiconductor region, a first electrode formed on the first passivation film and connected to the first conductive type semiconductor region through an opening portion formed in the first passivation film, a second passivation film on the second conductive type semiconductor region, and a second electrode formed on the second passivation film and connected to the second conductive type semiconductor region through an opening portion formed in the second passivation film.

Disclosed is a solar cell. The solar cell includes a semiconductor substrate, conductivity-type regions located in or on the semiconductor substrate, electrodes conductively connected to the conductivity-type regions, and insulating films located on at least one of opposite surfaces of the semiconductor substrate, and including a first film and a second film located on the first film, the second film has a higher carbon content than that of the first film, a refractive index of the second film is equal to or less than a refractive index of the first film, and an extinction coefficient of the second film is equal to or greater than an extinction coefficient of the first film.

A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

The invention relates to a method for producing a photovoltaic solar cell having at least one hetero-junction, including the following steps: A) providing a semiconductor substrate having base doping; B) producing a hetero-junction on at least one side of the semiconductor substrate, which hetero-junction has a doped hetero-junction layer and a dielectric tunnel layer arranged indirectly or directly between the hetero-junction layer and the semiconductor substrate; C) heating at least the hetero-junction layer in order to improve the electrical quality of the heterojunction. The invention is characterized in that, in a step D after step C, hydrogen is diffused into the hetero-junction layer and/or to the interface between the tunnel layer and the semiconductor substrate.

Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.

A preparation method for an N-type TOPCon cell comprising 1) texturing an N-type silicon wafer with an alkaline solution; 2) performing boron diffusion and laser lightly-doping on a front face of the wafer to form a lightly-doped region, and performing re-diffusion to form a front mask; 3) polishing a back face of the wafer; 4) performing three-in-one multi-layer thin film deposition on the back face of the wafer, to grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask; 5) performing high-temperature annealing under a preset high-temperature condition to form a doped polysilicon layer and activate doped phosphorus; 6) cleaning the front mask on the front face and back mask on the back face of the wafer; 7) depositing passivation films on the front face and back face of the N wafer; and 8) printing and sintering.