An electronic component mounting substrate includes: a metal substrate including a first surface, an insulation substrate including a second surface on which a first metal layer having a frame shape is provided, and a bonding material that bonds the first surface and the first metal layer. The bonding material is located in a region that includes the first metal layer and that is surrounded by the first metal layer in a plane perspective.

A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate.

A semiconductor device includes: a processor having a heat sink mounted thereon; and an optical module having a heat transfer interposer, wherein the heat sink and the optical module are coupled to each other via the heat transfer interposer.

And a semiconductor device includes: a semiconductor chip mounted on a substrate; a lead that covers the semiconductor chip; a heat sink installed on the lead; and an optical module coupled to the heat sink via a heat transfer interposer.

The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.

Disclosed is an integrated circuit (IC) chip incorporating a temperature-sensitive element and temperature stabilization circuitry for ensuring that the temperature of the temperature-sensitive element (TSE) remains essentially constant. The IC chip comprises a temperature-sensitive element and, within at least one region adjacent to the temperature-sensitive element, a first circuit that radiates a first heat amount to the TSE and a second circuit that radiates a second heat amount to the TSE. The second circuit senses changes in a first current amount in the first circuit and, thereby changes in the first heat amount. In response to those changes, the second circuit also automatically adjusts a second current amount in the second circuit and, thereby the second heat amount in order to ensure that the total heat amount radiated by the first circuit and the second circuit, in combination, to the TSE remains constant. Also disclosed is an associated method.

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

An image capture device includes an image sensor, a reading component, a timing generator, and a voltage regulator. The image sensor includes a temperature sensor configured to measure temperature measurements of the image sensor. The reading component is configured to read the temperature measurements from the temperature sensor. The timing generator is configured to apply an electronic shutter pulse to the image sensor. The voltage regulator is coupled between the temperature sensor and the reading component for regulating increased voltage at the reading component resulting from the electronic shutter pulse.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.