According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm.

The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

A semiconductor device includes an n.sup.+ type silicon carbide substrate, and in the substrate an active region where primary current flows and an edge termination area surrounding the active region. The semiconductor device has a first p-type region and a second p-type region in the edge termination area, and the first p-type region includes therein a plurality of third p-type regions, and the second p-type region includes therein a plurality of fourth p-type regions. The widths between the respective plurality of third p-type regions and the widths between the respective plurality of fourth p-type regions become greater further away from the active region.

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

A semiconductor element includes a base substrate that includes a Ga.sub.2O.sub.3-based crystal having a thickness of not less than 0.05 m and not more than 50 m, and an epitaxial layer that includes a Ga.sub.2O.sub.3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga.sub.2O.sub.3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.

A fingerprint sensing device includes a plurality of sensing units. Each sensing unit includes: a readout element, a photosensitive element, a light emitting element and a diode. The photosensitive element is electrically connected to the readout element. The light emitting element is disposed corresponding to the photosensitive element, and includes a first anode, a first cathode, and a light emitting layer located between the first anode and the first cathode. The diode includes a second anode and a second cathode, and a semiconductor layer located between the second anode and the second cathode. The second anode is electrically connected to the first cathode of the light emitting element, and the second cathode is electrically connected to the first anode of the light emitting element.

A semiconductor device includes a semiconductor chip having a source electrode on the front surface thereof, a diode that has an anode electrode on the front surface thereof, and a first conductive member through which output signals from the source electrode pass. The semiconductor device further includes a first wiring member that electrically connects the source electrode and the first conductive member, and a second wiring member that electrically connects the anode electrode and the first conductive member and that has a wider surface area than the first wiring member. The semiconductor device includes a second conductive member where the semiconductor chip and the diode are arranged.

A crystal laminate structure, in which crystals can be epitaxially grown on a -Ga.sub.2O.sub.3-based substrate with high efficiency to produce a high-quality -Ga.sub.2O.sub.3-based crystal film on the substrate; and a method for producing the crystal laminate structure are provided. The crystal laminate structure includes: a -Ga.sub.2O.sub.3-based substrate, of which the major face is a face that is rotated by 50 to 90 inclusive with respect to face; and a -Ga.sub.2O.sub.3-based crystal film which is formed by the epitaxial crystal growth on the major face of the -Ga.sub.2O.sub.3-based substrate.

The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

An embodiment semiconductor device includes an n type layer disposed on a first surface of a substrate, the n type layer including beta-gallium oxide (-Ga.sub.2O.sub.3), a p type layer disposed on the n type layer and including nickel oxide represented by a formula M.sub.yNi.sub.1-yO.sub.x, wherein M is a doping element, x is 0.8x1.0, and y is 0y<1, a first electrode disposed on the p type layer, and a second electrode disposed on a second surface of the substrate opposite the first surface.