Group-III nitride semiconductor device and method for fabricating the same

Abstract

The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

Claims

1. The method for fabricating a group-III nitride semiconductor device, comprising steps of: etching a stack structure with a depth between 250 nm and 1000 nm, and forming a first semiconductor stack structure and a second semiconductor stack structure; performing a first surface oxidation process; coating an ohmic metal layer, removing said ohmic metal layer, forming a first source and a first drain on said first semiconductor stack structure, and forming a second source and a second drain on said second semiconductor stack structure; defining fluorine-ion injection regions on said second semiconductor stack structure, and injecting fluorine ions; performing thermal treatment for fluorine ions and a second surface oxidation process; coating an insulating layer, etching said insulating layer, forming a first gate insulating layer between said first source and said first drain, and forming a second gate insulating layer between said second source and said second drain; coating a Schottky metal layer, removing said Schottky metal layer, forming a first gate on said first gate insulating layer, and forming a second gate on said second gate insulating layer; and coating a passivation film, and forming a plurality of openings on said passivation film corresponding to said first drain, said second gate, and said second source, respectively.

2. The method for fabricating of claim 1, wherein said stack structure comprises a channel layer, a barrier layer, and a cover layer.

3. The method for fabricating of claim 1, and further comprising: forming a third semiconductor stack structure and forming a protection diode on said third semiconductor stack structure while etching said stack structure; forming a negative electrode on said protection diode concurrently while removing said ohmic metal layer; and forming a positive electrode on said protection diode concurrently while removing said Schottky metal layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic diagram of the prior art;

(2) FIG. 2 shows a schematic diagram of forward recovery current;

(3) FIG. 3A shows a schematic diagram of the group-III nitride semiconductor device according to the first embodiment of the present invention;

(4) FIG. 3B shows a partially enlarged diagram of the group-III nitride semiconductor device according to the first embodiment of the present invention;

(5) FIGS. 4A to 4F show process steps according to the first embodiment of the present invention;

(6) FIG. 5A shows a top view of the group-III nitride semiconductor device according to the second embodiment of the present invention;

(7) FIG. 5B shows a cross-sectional view along the line segment V-V in FIG. 5A;

(8) FIG. 5C shows a cross-sectional view along the line segment V-V in FIG. 5A according to another embodiment;

(9) FIGS. 6A to 6E show process steps according to the second embodiment of the present invention;

(10) FIG. 7A shows a top view of the group-III nitride semiconductor device according to the third embodiment of the present invention;

(11) FIG. 7B shows a cross-sectional view along the line segment U-U in FIG. 7A;

(12) FIGS. 8A to 8F show process steps according to the third embodiment of the present invention; and

(13) FIG. 9 shows a schematic diagram of the group-III nitride semiconductor device according to the fourth embodiment of the present invention.

DETAILED DESCRIPTION

(14) In order to make the structure and characteristics as well as the effectiveness of the present invention to be further understood and recognized, the detailed description of the present invention is provided as follows along with embodiments and accompanying figures.

(15) Please refer to FIG. 3A, which shows a schematic diagram of the group-III nitride semiconductor device according to the first embodiment of the present invention. As shown in the figure, the group-III nitride semiconductor device comprises a substrate 10, a buffer layer 20, a semiconductor stack structure 30, and a passivation film 40. The buffer layer 20 is disposed on the substrate 10. The semiconductor stack structure 30 is disposed on the buffer layer 20 and comprises a plurality of electrodes, including a gate 31, a source 32, and a drain 33. In addition, a gate insulating layer 34 is disposed between the gate 31 and the semiconductor stack structure 30 for forming a HEMT. Besides, the passivation film 40 covers the HEMT and includes a plurality of openings W corresponding to the gate 31, the source 32, and the drain 33, respectively.

(16) The material of the substrate 10 is silicon; the material of the buffer layer 20 is gallium nitride; the materials of the semiconductor stack structure 30 are stacked gallium nitride and gallium aluminum nitride. The semiconductor stack structure 30 comprises a channel layer 301, a barrier layer 302, and a cover layer 303. Moreover, the present invention is not limited to the above materials.

(17) The material of the passivation film 40, which covers the HEMT, is silicon oxynitride, which has a refractive index between 1.46 and 1.98. By using oxynitride as the material of the passivation film 40, the deep traps at the interface between the passivation film 40 and the gallium aluminum nitride is reduced effectively and thus suppressing the surface leakage current as well as avoiding accumulation of excess charges that might lead to electrode burnout. In addition, trade-off should be made between the surface leakage current and the rate of current recovery. According to the lattice structure and the deep traps according to the present invention, the optimum refractive index of the oxynitride is between 1.46 and 1.98 with the optimum thickness greater than 100 nm. In addition to suppressing the surface leakage current, the device reliability is also increased under high-speed operations.

(18) There exists a parasitic SBD between the gate 31 and the source 32. If this parasitic SBD is turned on, a negative current is very possibly generated. Thereby, according to the present invention, the gate insulating layer 34 is disposed for preventing the negative current due to turning on of the parasitic SBD between the gate 31 and the source 32. In addition, in selecting the material of the gate insulating layer 34, the current collapse effect caused by charge accumulation at the defects under the gate 31 should be considered. Thereby, like the passivation film 40 as described above, oxynitride with a refractive index between 1.46 and 1.98 is selected as the material of the gate insulating layer 34. Alternatively, the voltage endurance can be considered. Please refer to FIG. 3B, which shows a partially enlarged diagram of the first embodiment. Silicon oxynitride combined with silicon oxide can be adopted. The gate insulating layer 34 includes a bottom part 341 and a top part 342. The bottom part 341 is silicon oxynitride with a thickness greater than 170 nm. The top part 342 is silicon oxide with a thickness greater than 500 nm. Besides, the length of the gate insulating layer 34 must be greater than that of the gate 31 for preventing effectively the current collapse effect.

(19) If the length of the gate 31 is too short, the forward current will be too small and the voltage endurance will be inferior. Then the gate 31 might burn out with ease. If the distance between the gate 31 and the source 32 is too close, the reverse voltage of the device is limited. Thereby, based on the above two considerations, the length of the gate 31 according to the present invention is greater than 6 um and the distance between the gate 31 and the source 32 is greater than 3 um. Hence, the forward current will be large; the gate 31 will not burn out; the device can endure a higher reverse voltage; and the device will not be damaged.

(20) Please refer to FIGS. 4A to 4F, which show process steps for the group-III nitride semiconductor device according to the first embodiment of the present invention. As shown in the figures, the steps comprises etching a stack structure 3 on a substrate 10 with a depth between 250 nm and 1000 nm and forming a semiconductor stack structure 30; performing a first surface oxidation process; coating an ohmic metal layer, removing the ohmic metal layer, and forming a source 32 and a drain 33; performing a second surface oxidation process; coating an insulating layer, etching the insulating layer, and forming a gate insulating layer 34 between the source 32 and the drain 33; coating a Schottky metal layer, removing the Schottky metal layer, and forming a gate 31 on the gate insulating layer 34; coating a passivation film 40, etching the passivation film 40, and forming a plurality of openings W on the passivation film 40 with the locations of the openings W corresponding to the gate 31, the source 32, and the drain 33, respectively.

(21) In the fabrication process, considering the materials of the passivation film 40 and the gate insulating layer 34 are both silicon oxynitride, while etching the stack structure 3, the depth is between 250 nm and 1000 nm. This is because while etching the stack structure 3, if the etching depth is deeper, more stress will be released by gallium nitride and gallium aluminum nitride. Then channel velocity changes and the reverse leakage current are increased accordingly. Besides, if the refractive index of the passivation film 40 is adjusted, the surface stress of the device is influenced as well. Thereby, when the passivation film 40 is silicon oxynitride and the refractive index is between 1.46 and 1.98, the optimum etching depth is between 250 nm and 1000 nm.

(22) In order to avoid dangling bonds or defects on the surface of the cover layer from forming paths for leakage current, according to the present invention, a surface oxidation process is used for patching the surface. The surface oxidation process is a high-temperature oxidation with temperatures between 400 and 800 C. Alternatively, a plasma oxidation method can be adopted. In the second surface oxidation process of the process flow, the surface oxide can be first kept. It can be removed while forming the gate insulating layer 34 in later steps.

(23) In addition to the above technical features, the group-III nitride semiconductor device according to the present invention can be formed along with the devices according to other embodiments of the present invention in the same process steps and on the same substrate. The other embodiments will be described later.

(24) In addition, if the HEMT according to the present embodiment is an enhancement-mode HEMT, only one step is added for injecting fluorine ions. Injection of fluorine ions can be performed using an inductively coupled plasma (ICP) process.

(25) Please refer to FIG. 5A and 5B. FIG. 5A shows a top view of the group-III nitride semiconductor device according to the second embodiment of the present invention; FIG. 5B shows a cross-sectional view along the line segment V-V in FIG. 5A. As shown in the figures, the group-III nitride semiconductor device according to the present invention comprises a substrate 10, a buffer layer 20, a first semiconductor stack structure 30A, a second semiconductor stack structure 30B, and a passivation film 40. The buffer layer 20 is disposed on the substrate 10. The first semiconductor stack structure 30A and the second semiconductor stack structure 30B are disposed on the buffer layer 20. The first semiconductor stack structure 30A comprises a plurality of electrodes, including a gate 31A, a source 32A, and a drain 33A. In addition, a gate insulating layer 34A is disposed between the gate 31A and the first semiconductor stack structure 30A for forming a HEMT using the first semiconductor stack structure 30A and the plurality of electrodes. The second semiconductor stack structure 30B comprises an anode 31B and a cathode 32B for forming a SBD. The anode 31B is connected to the gate 31A and the cathode 32B is connected to the drain 33A. In addition, the passivation film 40 covers the HEMT and the SBD, and includes a plurality of openings W corresponding to the source 32A and the anode 31B, respectively.

(26) The materials of the first semiconductor stack structure 30A and the second semiconductor stack structure 30B are stacked gallium nitride and gallium aluminum nitride. The first semiconductor stack structure 30A and the second semiconductor stack structure 30B comprise a channel layer 301, a barrier layer 302, and a cover layer 303, respectively. Moreover, the present invention is not limited to the above materials.

(27) The material of the passivation film 40 is silicon oxynitride with a refractive index between 1.46 and 1.98 and a thickness greater than 100 nm. By using the material of the passivation film 40, the surface leakage current of the device is reduced and the forward recovery current thereof is accelerated. This has been described above. The locations of the openings W of the passivation film 40 correspond to the source 32A and the anode 31B, respectively, for connection of the device to external circuits.

(28) The group-III nitride semiconductor device according to the second embodiment of the present invention includes the HEMT and the SBD. By using the HEMT to protect the SBD, the reverse breakdown voltage of the device is increased. In addition, thanks to the protection by the passivation film 40, the surface leakage current can be suppressed effectively and thus allowing the device to operate in high speed. Moreover, the HEMP can further be an enhancement-mode HEMT, as shown in FIG. 5C. By using the characteristic that an enhancement-mode HEMT requires a high turn-on voltage, the purpose of circuit protection can be achieved.

(29) Please refer to FIGS. 6A to 6E, which show process steps according to the second embodiment of the present invention. As shown in the figures, the steps comprises etching a stack structure 3 (not shown in the figures) on a substrate 10 with a depth between 250 nm and 1000 nm and forming a first semiconductor stack structure 30A and a second semiconductor stack structure 30B; performing a first surface oxidation process; coating an ohmic metal layer, removing the ohmic metal layer, forming a source 32A and a drain 33A on the first semiconductor stack structure 30A, forming a cathode 32B connected to the drain 33A on the second semiconductor stack structure 30B; performing a second surface oxidation process; coating an insulating layer, etching the insulating layer, and forming a gate insulating layer 34A between the source 32A and the drain 33A; coating a Schottky metal layer, removing the Schottky metal layer, forming a gate 31A on the gate insulating layer 34A, and forming an anode 31B connected to the gate 31A on the second semiconductor stack structure 30B; coating a passivation film 40, etching the passivation film 40, and forming a plurality of openings W on the passivation film 40 with the locations of the openings W corresponding to the source 32A and the anode 31B, respectively.

(30) The parameters and conditions of the second embodiment according to the present invention are identical to those of the first embodiment. Hence, the details will not be described again. According to the fabrication process of the second embodiment, the process can be performed in the same process of the first embodiment. Consequently, substantial time and costs can be saved.

(31) In addition, if the HEMT according to the present embodiment is an enhancement-mode HEMT, only one step is added for injecting fluorine ions. Injection of fluorine ions can be performed using an ICP process.

(32) Please refer to FIGS. 7A and 7B. FIG. 7A shows a top view of the group-III nitride semiconductor device according to the third embodiment of the present invention; FIG. 7B shows a cross-sectional view along the line segment U-U in FIG. 7A. As shown in the figures, the group-III nitride semiconductor device according to the present embodiment comprises a substrate 10, a buffer layer 20, a first semiconductor stack structure 30C, a second semiconductor stack structure 30D, and a passivation film 40. The buffer layer 20 is disposed on the substrate 10. The first semiconductor stack structure 30C is disposed on the buffer layer 20 and comprises a plurality of electrodes, including a first gate 31C, a first source 32C, and a first drain 33C. In addition, a first gate insulating layer 34C is disposed between the first gate 31C and the first semiconductor stack structure 30C for forming a first HEMT. The second semiconductor stack structure 30D comprises a plurality of electrodes, including a second gate 31D, a second source 32D, and a second drain 33D. In addition, a second gate insulating layer 34D is disposed between the second gate 31D and the second semiconductor stack structure 30D for forming a second HEMT. The first gate 31C is connected to the second source 32D and the first source 32C is connected to the second drain 33D. Furthermore, the passivation film 40 covers the first HEMT and the second HEMT, and includes a plurality of openings W corresponding to the first drain 33C, the second gate 31D, and the second source 32D, respectively.

(33) The materials of the first semiconductor stack structure 30C and the second semiconductor stack structure 30D are stacked gallium nitride and gallium aluminum nitride. The first semiconductor stack structure 30C and the second semiconductor stack structure 30D comprise a channel layer 301, a barrier layer 302, and a cover layer 303, respectively. Moreover, the present invention is not limited to the above materials.

(34) The material of the passivation film 40 is silicon oxynitride with a refractive index between 1.46 and 1.98 and a thickness greater than 100 nm. By using the material of the passivation film 40, the surface leakage current of the device is reduced and the forward recovery current thereof is accelerated. This has been described above. The locations of the openings W of the passivation film 40 correspond to the first drain 33C, the second gate 31D, and the second source 32D, respectively, for connection of the device to external circuits.

(35) The group-III nitride semiconductor device according to the third embodiment of the present invention can be a mixed mode device. That is to say, one of the first and second HEMTs is a depletion-mode HEMT and the other is an enhancement-mode HEMT. By coupling HEMTs of different modes, the reverse breakdown voltage of the device can be increased. Besides, with the protection of the passivation film 40, the surface leakage current can be suppressed effectively. Then multiple HEMTs can be connected in series for achieving the purpose of enduring high voltages. Furthermore, when the present invention is applied in the mixed mode, the depletion-mode HEMT is a normally-on device. It requires a sufficient negative voltage at the gate to be turned off. On the contrary, the enhancement-mode HEMT requires a positive voltage for operation. When it operates, there is a channel resistance. Thereby, a sufficient positive voltage applied to the enhancement-mode HEMT can turn on the depletion-mode HEMT as well. In addition, according to experiments, when the gate widths of two HEMTs are identical, the current in an enhancement-mode HEMT will be higher than that in a depletion-mode HEMT. Thereby, while fabricating the device according to the present invention, the gate width of the depletion-mode HEMT should be made wider than that of the enhancement-mode one. Otherwise, the current will be limited by the depletion-mode HEMT. According to experiments, when the ratio of the width of the enhancement-mode HEMT to that of the depletion-mode one is 1:3, ideal operating currents will be given.

(36) Please refer to FIGS. 8A to 8F, which show process steps according to the third embodiment of the present invention. As shown in the figures, the steps comprises etching a stack structure 3 (not shown in the figures) on a substrate 10 with a depth between 250 nm and 1000 nm and forming a first semiconductor stack structure 30C and a second semiconductor stack structure 30D; performing a first surface oxidation process; coating an ohmic metal layer, removing the ohmic metal layer, forming a first source 32C and a first drain 33C on the first semiconductor stack structure 30C, forming a second source 32D and a second drain 33D on the second semiconductor stack structure 30D, and the first source 32C connected to the second drain 33D; defining fluorine-ion injection regions F on the second semiconductor stack structure 30D, and injecting fluorine ions; performing thermal treatment for fluorine ions and a second surface oxidation process; coating an insulating layer, etching the insulating layer, forming a first gate insulating layer 34C between the first source 32C and the first drain 33C, and forming a second gate insulating layer 34D between the second source 32D and the second drain 33D to prevent Schottky metal direct contact to 30D which will create a Schottky diode between the second gate 31D and the second source 32D, when a voltage is given, the Schottky diode between the second gate 31D and the second source 32D will turn on; coating a Schottky metal layer, removing the Schottky metal layer, forming a first gate 31C on the first gate insulating layer 34C, forming a second gate 31D on the second gate insulating layer 34D, and the first gate 31C connected to the second source 32D; coating a passivation film 40, etching the passivation film 40, and forming a plurality of openings W on the passivation film 40 with the locations of the openings W corresponding to the first drain 33C, the second gate 31D, and the second source 32D, respectively.

(37) The parameters and conditions of the third embodiment according to the present invention are identical to those of the first embodiment. Hence, the details will not be described again. According to the fabrication process of the third embodiment, the process can be performed in the same processes of the first and second embodiments. Consequently, substantial time and costs can be saved. In addition, the gate insulating layer allows the process to have thermal treatment of higher temperatures; and injection of fluorine ions can be performed using an ICP process.

(38) Please refer to FIG. 9, which shows a schematic diagram of the group-III nitride semiconductor device according to the fourth embodiment of the present invention. As shown in the figure, the group-III nitride semiconductor device according to the present invention can combine a protection diode in the previous embodiments. For example, according to the first embodiment, the group-III nitride semiconductor device further comprises a second semiconductor stack structure 30F, a second buffer layer 304, an n-type doping layer 501, an intrinsic layer 502, a p-type doping layer 503, a positive electrode 51, and a negative electrode 52. The n-type doping layer 501, the intrinsic layer 502, and the p-type doping layer form a PIN diode, which can be used for protecting HEMT or SBD.

(39) Although the reverse breakdown voltage of a PIN diode is lower than that of a HEMT, a PIN diode owns the recoverable property. This property enables a PIN diode to continue operating aster breakdown. Contrarily, a HEMT is unrecoverable after breakdown. By using this property in circuit designs, PIN diodes can act as protection devices that reach breakdown first at reverse biases and thus protecting HEMTs.

(40) The fabrication of protection diodes can be combined with the processes according to the previous embodiments. For example, in the process according to the first embodiment, while etching the stack structure 3, a second semiconductor stack structure 30F can be formed concurrently. A protection diode is then formed on the second semiconductor stack structure 30F. While removing the ohmic metal layer, a negative electrode 52 is formed on the protection diode. While etching the Schottky metal layer, a positive electrode 51 is formed on the protection diode. Accordingly, in a single process flow, a protection diode can be fabricated. This helps saving time and costs.

(41) The group-III nitride semiconductor device according to the present invention includes a HEMT, which includes a passivation film covering thereon. The material of the passivation film 40 is silicon oxynitride with a refractive index between 1.46 and 1.98. By using oxynitride as the material of the passivation film, the deep traps at the interface between the passivation film and the gallium aluminum nitride is reduced effectively and thus suppressing the surface leakage current as well as avoiding accumulation of excess charges that might lead to electrode burnout. In addition, the rate of forward current recovery is accelerated, so that the device reliability is increased under high-speed operations. The material of the gate insulating layer of the HEMT is also silicon oxynitride with a refractive index between 1.46 and 1.98. Alternatively, the gate insulating layer can be divided into a top part and a bottom part, with materials of silicon oxide and silicon oxynitride, respectively. The purpose is to avoid current breakdown effect and to increase the voltage endurance of the gate electrode. The length of the gate according to the present invention is greater than 6 um and the distance between the gate and the source is greater than 3 um. Hence, the forward current will be increased. As a consequence, the device can endure a higher reverse voltage and the device will not be damaged. According to the second embodiment, a SBD is further included for increasing the reverse breakdown voltage of the device. According to the third embodiment, HEMTs of different modes are included for achieving the efficacy of increasing reverse breakdown voltage. According to the fourth embodiment, a protection diode is further includes for protecting the device from occurring unrecoverable condition caused by reverse breakdown. In addition, the process according to each embodiment can be completed on a single substrate concurrently. This helps saving substantial time and costs.

(42) Accordingly, the present invention conforms to the legal requirements owing to its novelty, nonobviousness, and utility. However, the foregoing description is only embodiments of the present invention, not used to limit the scope and range of the present invention. Those equivalent changes or modifications made according to the shape, structure, feature, or spirit described in the claims of the present invention are included in the appended claims of the present invention.