Patent classifications
H10D8/60
Semiconductor device
In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.
P-DOPING OF GROUP-III-NITRIDE BUFFER LAYER STRUCTURE ON A HETEROSUBSTRATE
An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 11018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.
METHOD FOR TREATING A GALLIUM NITRIDE LAYER COMPRISING DISLOCATIONS
A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.
SEMICONDUCTOR DEVICE
A semiconductor device includes a SiC layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first SiC region of a first conductivity type in the SiC layer, a second SiC region of a second conductivity type in the SiC layer and surrounding a portion of the first SiC region, a third SiC region of the second conductivity type in the SiC layer and surrounding the second SiC region, the third SiC region having an impurity concentration of the second conductivity type lower than that of the second SiC region, and a fourth SiC region of the second conductivity type in the SiC layer between the second SiC region and the third Sic region, the fourth SiC region having an impurity concentration of the second conductivity type higher than that of the second SiC region.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
This semiconductor device includes: a semiconductor layer (6) that is formed of first conductivity-type SiC; a plurality of trenches (8) that are formed in the semiconductor layer; second conductivity-type column regions (12) that are formed along the inner surfaces of the trenches; a first conductivity-type column region (13) that is disposed between the adjacent second conductivity-type column regions; and insulating films (14) that are embedded in the trenches. The semiconductor device is capable of improving a withstand voltage by means of a super junction structure. The semiconductor device may also include an electric field attenuation section (16) for attenuating electric field intensity of a surface section of the first conductivity-type column region (13).
SEMICONDUCTOR DEVICE
According to one embodiment, in a semiconductor device, The first semiconductor region is provided between the first and the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The first and second connection region are electrically connected to the second electrode, reaches the first semiconductor region. The first insulating film is provided between the first connection region and the second semiconductor region and between the first connection region and the first semiconductor region. The second insulating film is provided between the second connection region and the second semiconductor region and between the second connection region and the first semiconductor region. The third connection region is provided between the first connection region and the second connection region, the third connection region is electrically connected to the second electrode, reaches the first semiconductor region or reaches the second semiconductor region.
SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a first electrode, a second electrode, a semiconductor substrate having a first plane, a second plane, a first conductivity-type first region, and a plurality of second conductivity-type second regions provided around the first electrode, the second regions being in contact with the first plane, at least a portion of the semiconductor substrate being provided between the first electrode and the second electrode, a first insulating film provided on or above the second regions, the first insulating film including positive charges, and a second insulating film provided on or above the second regions, second insulating film including negative charges.
SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface.
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND POWER CONVERTER
There is provided a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device comprises a process of forming a semiconductor layer that is mainly made of a group III nitride and has n-type characteristics, by crystal growth; a film formation process of forming a through film that is mainly made of an element different from an element serving as an n-type impurity relative to the group III nitride, by growth on the semiconductor layer continuous with crystal growth of the semiconductor layer; an ion implantation process of implanting a p-type impurity into the semiconductor layer across the through film by ion implantation; a heating process of heating the semiconductor layer and the through film after completion of the ion implantation process, so as to activate a region of the semiconductor layer in which the p-type impurity is ion-implanted, to a p-type semiconductor region; and a removal process of removing the through film from the semiconductor layer, after completion of the heating process. This configuration improves the surface morphology of the p-type semiconductor region formed by ion implantation.