A high-density three-dimensional memory device with interconnection of low resistance and a manufacturing method thereof are provided. The device includes an underlying circuit part, and a base structure disposed on the underlying circuit part. The base structure includes first conductive medium layers and insulating medium layers which are alternately stacked on each other from bottom to top. The base structure has dendritic interdigitated structure, the dendritic interdigitated structure is composed of two dendritic structures. The dendritic structure includes a trunk and branches connected to and perpendicular to the trunk. A preset number of memory holes are formed in a curved division trench between the branches and an external structure. A vertical electrode perpendicular to the bottom surface of the base structure is disposed in the memory hole, a storage medium required for a preset memory type is disposed between the vertical electrode and an inner wall of the memory hole.

A high-density three-dimensional memory device with interconnection of low resistance and a manufacturing method thereof are provided. The device includes an underlying circuit part, and a base structure disposed on the underlying circuit part. The base structure includes first conductive medium layers and insulating medium layers which are alternately stacked on each other from bottom to top. The base structure has dendritic interdigitated structure, the dendritic interdigitated structure is composed of two dendritic structures. The dendritic structure includes a trunk and branches connected to and perpendicular to the trunk. A preset number of memory holes are formed in a curved division trench between the branches and an external structure. A vertical electrode perpendicular to the bottom surface of the base structure is disposed in the memory hole, a storage medium required for a preset memory type is disposed between the vertical electrode and an inner wall of the memory hole.

Method of forming a metal-semiconductor contact, comprising the steps of: forming, on a semiconductor body having a first electrical conductivity, a first metal layer; performing a thermal treatment of at least a portion of the first metal layer by a LASER beam having an incidence direction on the first metal layer, including heating the portion of the first metal layer, along said incidence direction, at a temperature between 1500 C. and 3000 C.

A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

A multilayered semiconductor device including a substrate including n-type or p-type doped silicon carbide (SiC), an epitaxial oxide layer above the substrate, and a metal layer above the epitaxial oxide layer. In some cases, the epitaxial oxide layer includes n-type conductivity and the substrate is p-type doped, and the substrate and the epitaxial oxide layer form a p/n junction. In some cases, the device can further include an epitaxial transition layer between the substrate and the epitaxial oxide layer, where the epitaxial transition layer includes an n-type doping density that is at least an order of magnitude greater than an n-type doping density of the epitaxial oxide layer. In some cases, the substrate can be a composite substrate including a surface layer including single crystal SiC on a polycrystalline SiC layer. In some cases, a second metal layer is in contact with the substrate.

A multilayered semiconductor device including a substrate including n-type or p-type doped silicon carbide (SiC), an epitaxial oxide layer above the substrate, and a metal layer above the epitaxial oxide layer. In some cases, the epitaxial oxide layer includes n-type conductivity and the substrate is p-type doped, and the substrate and the epitaxial oxide layer form a p/n junction. In some cases, the device can further include an epitaxial transition layer between the substrate and the epitaxial oxide layer, where the epitaxial transition layer includes an n-type doping density that is at least an order of magnitude greater than an n-type doping density of the epitaxial oxide layer. In some cases, the substrate can be a composite substrate including a surface layer including single crystal SiC on a polycrystalline SiC layer. In some cases, a second metal layer is in contact with the substrate.

In some embodiments, the techniques described herein relate to a multilayered semiconductor diode device including: a substrate including silicon carbide (SiC); an epitaxial drift layer including a first semiconductor oxide material or SiC on the substrate; an epitaxial channel layer including a second semiconductor oxide material on the epitaxial drift layer; and a metal layer above the epitaxial drift layer to form a Schottky barrier junction. The epitaxial channel layer and the Schottky metal layer form a mesa structure contacting a sidewall layer. In some embodiments, a method of forming a multilayered semiconductor diode device includes: providing a substrate including silicon carbide (SiC); forming an epitaxial drift layer; forming an epitaxial channel layer; forming a metal layer to form a Schottky barrier junction; etching the epitaxial channel layer and the metal layer to form a mesa structure; and forming a sidewall layer contacting a wall of the mesa structure.

A semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions, silicide films, and a first electrode; the termination region has a second second-conductivity-type region. The active region is configured by ohmic regions where the first electrode is in contact with the silicide films, and Schottky regions where the first electrode is in contact with the first-conductivity-type region. When a doping concentration of the first-conductivity-type region is a low concentration, a greater number of the ohmic regions is provided in a chip center portion than in a chip outer peripheral portion and when the doping concentration of the first-conductivity-type region is a high concentration, a greater number of the ohmic regions is provided in the chip outer peripheral portion than in the chip center portion.

Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.