H10D8/60

SEMICONDUCTOR DEVICE WITH NON-UNIFORM TRENCH OXIDE LAYER
20170271498 · 2017-09-21 ·

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

Controlled ion implantation into silicon carbide using channeling and devices fabricated using controlled ion implantation into silicon carbide using channeling
09768259 · 2017-09-19 · ·

Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300 C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000 C.-hours to activate the implanted ions.

SEMICONDUCTOR DEVICE COMPRISING PN JUNCTION DIODE AND SCHOTTKY BARRIER DIODE
20170263590 · 2017-09-14 · ·

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

OXIDE SEMICONDUCTOR SUBSTRATE AND SCHOTTKY BARRIER DIODE

A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.

LOW-COST SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

MPS DIODE
20170256657 · 2017-09-07 ·

There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are arranged alternately on one surface of the first semiconductor layer; and a Schottky electrode that is in Schottky junction with the N-type semiconductor regions and is arranged to be adjacent to and in contact with at least part of the P-type semiconductor regions. A donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the first semiconductor layer is lower than the donor concentration in an area of the first semiconductor layer that is adjacent to and in contact with the N-type semiconductor region and is lower than the donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the Schottky electrode. This configuration improves a breakdown voltage under applying a reverse bias voltage and reduces a rising voltage under applying a forward bias voltage.

SCHOTTKY DIODE AND MANUFACTURING METHOD OF THE SAME
20170256656 · 2017-09-07 ·

Provided herein is a Schottky diode including: a first semiconductor layer; an intermediate layer provided over the first semiconductor layer; a second semiconductor layer provided over the intermediate layer; an anode provided over the second semiconductor layer; and a cathode provided over the first semiconductor layer, wherein in a sectional view, a width of the second semiconductor layer is greater than a width of the intermediate layer.

Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.410.sup.17 cm.sup.3 or higher and 610.sup.17 cm.sup.3 or lower and an impurity concentration in a second JTE region is set to 210.sup.17 cm.sup.3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 610.sup.17 cm.sup.3 or higher and 810.sup.17 cm.sup.3 or lower and an impurity concentration in the second JTE region is set to 210.sup.17 cm.sup.3 or lower in a case of a junction barrier Schottky diode.

Method for treating a semiconductor wafer

A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum.