An image sensor includes a pixel array; a logic circuit configured to convert an image signal generated from the pixel array during a first period into image data; and a memory. The image data may be written in the memory during a second period, of which at least a portion overlaps the first period. The logic circuit may write dummy data in the memory during a third period overlapping the first period and not overlapping the second period.

Provided is a photoelectric conversion device including a pixel array in which pixels, each of the pixels including a photoelectric conversion element, are arranged in columns, a signal line that is arranged corresponding to one of the columns in the pixel array and to which a signal from the pixel is output, a current source configured to supply the signal line with a driving current; a current adjusting unit configured to control the driving current into a current amount including a first current amount and a second current amount greater than the first current amount, and an assisting element configured to assist a change in a current flowing through the signal line when the driving current changes from the first current amount to the second current amount. The first current amount is a current amount in a state where the driving current is disconnected.

Techniques are described for sampled bandgap reference generation for CMOS image sensor (CIS) applications. For example, the CIS includes a pixel array, one or more pixel analog to digital converters (ADCs), and a sampled bandgap reference generator, all integrated in close proximity on a chip. The ADCs rely on stable reference levels from the bandgap reference generator for performing pixel conversions for the pixel array. Embodiments of the sampled bandgap reference generator can operate according to reference generation cycles. Each cycle can include a first portion, in which an active core dynamically stabilizes the bandgap reference level; and a second portion, in which the core is deactivated, and the bandgap reference level is output based on a sampled level obtained during the preceding first portion of the cycle. The cycle timing can be controlled to achieve sufficient dynamic stabilization of the reference levels, while mitigating photon emissions from the core.

Techniques are described for efficient staggered high-dynamic-range (HDR) output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided upsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. In each image capture time window, multiple (e.g., three) luminance-enhanced (LE) component images are generated. Each LE component image is generated by exposing the image sensor to incident illumination for a respective amount of time, using pixel binning during readout to generate appreciably downsampled color and luminance capture frames, generating an upsampled luminance guide frame from the luminance capture frame, and using the upsampled luminance guide frame to guide upsampling (e.g., and remosaicking) of the color capture frame. The resulting LE components images can be digitally combined to generate an HDR output image.

An imaging device includes a first substrate, a second substrate, a third substrate, and a switching unit. The first substrate has a pixel including a photodiode and floating diffusion that holds the charge converted by the photodiode. The second substrate has a pixel circuit that reads out a pixel signal based on the charge held in the floating diffusion in the pixel, and is stacked on the first substrate. The third substrate has a processing circuit that detects a pixel signal read out by the pixel circuit, and is stacked on the second substrate. The switching unit is provided to enable electrical connection between the floating diffusion and a floating diffusion of another pixel in the first substrate, and is provided on the second substrate. As a result, by switching the capacitance of the floating diffusion of the pixel using floating diffusion of another pixel, it is possible to switch the charge-voltage conversion efficiency levels.

Solid-state imaging elements that prevent deterioration of image quality, and reduce power consumption and AD-conversion time are disclosed. In one example, a solid-state imaging element includes a first comparator that uses a first voltage corresponding to an input voltage received from a first pixel, in reference to a first voltage difference between the input voltage and a first reference voltage, and that outputs a comparison result between the input voltage and the first reference voltage in reference to a second voltage difference, and a second comparator that outputs a comparison result of comparison between the input voltage and the second reference voltage in reference to a fourth voltage difference.

There is provided a pixel circuit including a first circuit and a second circuit. The first circuit is used to output a first voltage associated with exposure intensity. The second circuit is used to output a second voltage associated with exposure time interval. The processor multiples the first voltage to a ratio between a reference voltage and the second voltage to obtain an actual light intensity, wherein the reference voltage is a voltage value outputted by the second circuit of a dummy pixel.

A ramp generator includes a plurality of switched current sources coupled in parallel between a resistor and ground. A digital ramp control signal generator includes a counter to generate a ramp control signal in response to a clock signal. Each bit of the ramp control signal is coupled to control switching of a respective one of the plurality of switched current sources to generate a ramp signal at an output of the ramp generator. The digital ramp control signal generator is coupled to receive a reset signal to zero the ramp control signal. The digital ramp control signal generator is further coupled to receive a set bits signal to initialize the ramp signal to a preset value after every reset of the ramp control signal to add a DC offset compensation current determined by the preset value to the ramp signal.

A sensor system includes a sensor array and a gradation determination section. The sensor array includes a first sensor and a second sensor. The first sensor is configured to detect, with a first sensitivity, a variation in a quantity of light at a first pixel address. The second sensor is configured to detect, with a second sensitivity that is lower than the first sensitivity, a variation in a quantity of light at a second pixel address that is adjacent to or coincides with the first pixel address. The gradation determination section is configured to determine, when the first sensor generates a first event signal in response to a luminance variation event, a gradation of an object having caused the luminance variation event to occur, depending on whether or not the second sensor generates a second event signal in response to the luminance variation event.

Imager readout circuit comprising: an active reset stage of the integration capacitor equipped with a first current amplifier, a buffered direct injection bias stage of the photodetector equipped with transistors forming a second current amplifier, a switching circuit comprising a coupling stage integrated in the readout circuit, the switching circuit being controlled by control signals and being configured to: during a reset phase of the integration capacitor corresponding to a first state of said control signals: couple said first current source to the integration capacitor and activate the first current amplifier while uncoupling said second current source of the photodetector and deactivating the second amplifier, during an integration phase of a current from the photodiode and corresponding to a second state of said control signals, couple said second current source to the photodetector and activate the second current amplifier while uncoupling said first current source of the integration capacitor and deactivating the first amplifier.