The reading accuracy of an imaging device is increased. Clear image capturing is performed even in the case where the luminance is high. A reading circuit of the imaging device includes an amplifier portion and a conversion portion. The amplifier portion amplifies a potential difference between a first signal and a second signal that are sequentially input and outputs the amplified difference to the conversion portion. The conversion portion converts the output potential of the amplifier portion into a digital value. The amplifier portion is reset on the basis of a first reference potential and the first signal and amplifies the potential difference on the basis of a second reference potential that is different from the first reference potential and the second signal.

Provided are a vision sensor, an image processing device including the vision sensor, and an operating method of the vision sensor. The vision sensor includes a plurality of pixels arranged in a matrix form, wherein each of the plurality of pixels includes: a sensing circuit configured to output an output voltage by sensing a change of light; a comparison circuit configured to output a comparison signal indicating whether an event has occurred by comparing the output voltage to an event threshold; and an event detection circuit configured to generate internal event signals by sampling the comparison signal at each of a plurality of sampling time points, and configured to output a valid event signal based on the internal event signals.

An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion receives charge transferred from the first and second photodiodes. An analog to digital converter (ADC) performs a first ADC conversion to generate a reference readout in response to charge in the shared floating diffusion after a reset operation. The ADC is next performs a second ADC conversion to generate a first half of a phase detection autofocus (PDAF) readout in response to charge transferred from the first photodiode to the shared floating diffusion. The ADC then performs a third ADC conversion to generate a full image readout in response to charge transferred from the second photodiode combined with the charge transferred previously from the first photodiode in the shared floating diffusion.

An image sensor includes a pixel array including a plurality of pixels; a row driver configured to control the plurality of pixels; and an analog-to-digital converter configured to digitize a result sensed by the pixel array to generate a first image, wherein the pixel array includes: first pixel groups, wherein each first pixel group of the first pixel groups includes first white pixels and first color pixels among the plurality of pixels; and second pixel groups, wherein each second pixel group of the second pixel groups includes second white pixels and second color pixels among the plurality of pixels, and wherein first pixel data of the first image are generated based on the first white pixels and the first color pixels, and second pixel data of the first image are generated based on the second color pixels.

An electronic device comprising circuity configured to integrate charge collected by at least two floating diffusions on at least one capacitor and to change the direction of charge integration from a first current flow direction to a second current flow direction between a first integration phase and a second integration phase.

An image sensor includes: a photoelectric conversion unit that photoelectrically converts light to generate an electric charge; a holding unit that holds the electric charge generated by the photoelectric conversion unit; an accumulation unit that accumulates the electric charge generated by the photoelectric conversion unit; a first transfer path that transfers the electric charge generated by the photoelectric conversion unit to the accumulation unit; and a second transfer path that transfers the electric charge generated by the photoelectric conversion unit to the accumulation unit via the holding unit.

An imaging panel is provided. The imaging panel includes a photoelectric conversion element, a pixel, a first conductive film, a second conductive film, a third conductive film, a fourth conductive film, and a fifth conductive film. The pixel includes a pixel circuit and supplies an image signal. The first conductive film is supplied with the image signal and the photoelectric conversion element includes a first terminal connected to the second conductive film and a second terminal connected to the pixel circuit. The pixel circuit includes a first switch, a second switch, a third switch, a transistor, and a capacitor. The first switch includes a terminal connected to the second terminal of the photoelectric conversion element and a terminal connected to a node. The transistor includes a gate electrode connected to the node and a first electrode connected to the third conductive film. The second switch includes a terminal connected to a second electrode of the transistor and a terminal connected to the first conductive film. The third switch includes a terminal connected to the fourth conductive film and a terminal connected to the node. The capacitor includes a first electrode connected to the node and a second electrode connected to the fifth conductive film.

A photoelectric converter includes pixels, vertical output lines to which a signal is outputted from the pixels, clippers configured to limit a potential of the output lines and a controller. Each of the clippers includes a first circuit configured to output an amplification signal according to a predetermined potential and the potential of the output line and a second circuit configured to supply a current according to the amplification signal to the output line. The controller controls each of the clippers to a state selected from states including a first state in which a range in which the potential of the output line can change is limited using the first and second circuits, and a second state in which the range in which the potential of the vertical output line can change is limited with an output of the second circuit deactivated.

Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).

A solid-state imaging device includes a plurality of pixel cells, each of the pixel cells including a light receiving element, a floating diffusion, a first source follower circuit, and a second source follower circuit. The plurality of pixel cells are connected to an output signal line. The light receiving element photoelectrically converts incident light, and stores a signal charge. The floating diffusion converts the signal charge read out of the light receiving element into a signal voltage. The first source follower circuit is connected to the floating diffusion, and outputs an output voltage corresponding to the signal voltage. The second source follower circuit is connected in series with the first source follower circuit, and outputs a pixel signal corresponding to the output voltage.