A display device includes a display panel including a plurality of pixels connected to data lines and sensing lines, a data driver including a plurality of buffer amplifiers which supplies a first sensing voltage to the data lines during a first sensing period and a sensor which receives a first sensing signal from the pixels through the sensing lines during the first sensing period, and a global amplifier which supplies a second sensing voltage to the data lines during a second sensing period different from the first sensing period. The sensor receives a second sensing signal corresponding to the second sensing voltage from the pixels through the sensing lines during the second sensing period, and generates compensation data based on a difference value between the first sensing signal and the second sensing signal.

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.

An image sensor having photosites forming an array (K×L) of K rows and L columns, including a first set of integrator circuits, with a first regulation by analog weighting in blocks of n×n′ photosites, said photosites belonging to n adjacent columns and to n′ adjacent rows, and a second set of integrator circuits, with a second regulation by analog weighting in blocks of m×m′ photosites, said photosites belonging to m adjacent columns and to m′ adjacent rows, n adjacent columns of a first set of columns of the array being connected to n×n′ integrator circuits of the first set, m adjacent columns of a second set of columns of the array being connected to m×m′ integrator circuits of the second set, n columns of the first set alternating with m columns of the second set to form the array of photosites.

An imaging device that makes it possible to smoothly transfer electric charges from a photoelectric converter to a transfer destination is provided. This imaging device includes: a semiconductor layer having a front surface and a back surface, the back surface being on an opposite side of the front surface; photoelectric converter that is embedded in the semiconductor layer and generates electric charges corresponding to a received light amount; and a transfer section that includes a first trench gate and a second trench gate and transfers the electric charges from the photoelectric converter to a single transfer destination via the first trench gate and the second trench gate, the first trench gate and the second trench gate each extending from the front surface to the back surface of the semiconductor layer into the photoelectric converter. The first trench gate has a first length from the front surface to the photoelectric converter, and the second trench gate has a second length from the front surface to the photoelectric converter, the second length being shorter than the first length.

Ones of row addresses and column addresses of pixels in a first group are the same as those of a second group. A range of the others of the row addresses and the column addresses of the first group excludes that of the second group. A range of the others of row addresses and column addresses is included in a range of the others of the row addresses and the column addresses of the first and second groups. A portion of the range of the row addresses and the column addresses of the first group overlaps with that of the third group, and the other portion of the range of the first group does not overlap with that of the third group. Intra-group addition signals of the first, second, and third groups are obtained.

An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

A photoelectric conversion apparatus includes a semiconductor substrate including recessed portions and insulators disposed on the respective recessed portions. The semiconductor substrate includes a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region that is of a conductivity type different from the first-conductivity-type and that is formed in the first semiconductor region, a second-conductivity-type third semiconductor region in contact with the second semiconductor region on a surface of the semiconductor substrate, and a first-conductivity-type fourth semiconductor region that includes the recessed portions. The second semiconductor region and the third semiconductor region are surrounded by the fourth semiconductor region on the surface of the semiconductor substrate. The insulators on the recessed portions extend through the fourth semiconductor region and are in contact with the first semiconductor region.

An image sensor for detecting light-emitting diode (LED) without flickering includes a pixel array with pixels. Each pixel including subpixels including a first and a second subpixel, dual floating diffusion (DFD) transistor, and a capacitor coupled to the DFD transistor. First subpixel includes a first photosensitive element to acquire a first image charge, and a first transfer gate transistor to selectively transfer the first image charge from the first photosensitive element to a first floating diffusion (FD) node. Second subpixel includes a second photosensitive element to acquire a second image charge, and a second transfer gate transistor to selectively transfer the second image charge from the second photosensitive element to a second FD node. DFD transistor coupled to the first and the second FD nodes. Other embodiments are also described.

A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

The present disclosure provides an image sensor and an image collection system. The image sensor includes: a pixel collection circuitry array including a plurality of pixel collection circuitries, each pixel collection circuitry being configured to monitor a change in a light intensity in a field of view and enter a triggered state when the change in the light intensity meets a predetermined condition; a boundary triggered pixel determination array configured to determine a boundary triggered pixel collection circuitry in the pixel collection circuitries in the triggered state; and a reading unit configured to respond to the boundary triggered pixel collection circuitry and output address information about the boundary triggered pixel collection circuitry.