An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

The present disclosure relates to an image pickup device and an electronic apparatus that enable further downsizing of device size. The device includes: a first structural body and a second structural body that are layered, the first structural body including a pixel array unit, the second structural body including an input/output circuit unit, and a signal processing circuit; a first through-via, a signal output external terminal, a second through-via, and a signal input external terminal that are arranged below the pixel array, the first through-via penetrating through a semiconductor substrate constituting a part of the second structural body, the second through-via penetrating through the semiconductor substrate; a substrate connected to the signal output external terminal and the signal input external terminal; and a circuit board connected to a first surface of the substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.

An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.

The present invention provides a single photon avalanche diode device. The device has a logic substrate comprising an upper surface. The device has a sensor substrate bonded to an upper surface of the logic substrate. In an example, the sensor substrate comprises a plurality of pixel elements spatially disposed to form an array structure. In an example, each of the pixel elements has a passivation material, an epitaxially grown silicon material, an implanted p-type material configured in a first portion of the epitaxially grown material, an implanted n-type material configured in a second portion of the epitaxially grown material, and a junction region configured from the implanted p-type material and the implanted n-type material.

An imaging device includes an imaging unit including a plurality of pixels, respectively including photoelectric converters and charge accumulation nodes that accumulate signal charge. The imaging unit outputs image data based on signals corresponding to the signal charge accumulated in the charge accumulators. The imaging device includes an image processing unit that processes the image data output by the imaging unit. The imaging unit sequentially outputs a plurality of pieces of image data in one frame period by performing readout nondestructively. The image processing unit generates difference image data by determining a difference between two pieces of image data, selects output image data from initial image data and the difference image data, and combines the output image data and normal readout image data included in the plurality of pieces of image data, to generate combination-result image data.

A solid-state imaging element of the present disclosure a pixel. The pixel includes a charge accumulation unit that accumulates a charge photoelectrically converted by a photoelectric conversion unit, a reset transistor that selectively applies a reset voltage to the charge accumulation unit, an amplification transistor having a gate electrode electrically connected to the charge accumulation unit, and a selection transistor connected in series to the amplification transistor. Additionally, the solid-state imaging element includes a first wiring electrically connecting the charge accumulation unit and the gate electrode of the amplification transistor, a second wiring electrically connected to a common connection node of the amplification transistor and the selection transistor and formed along the first wiring, and a third wiring electrically connecting the amplification transistor and the selection transistor.

An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.

A second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel and a third substrate including a processing circuit that performs signal processing on the pixel signal are provided. The first substrate, the second substrate, and the third substrate are stacked in this order. A semiconductor layer including the pixel circuit is divided by an insulating layer. The insulating layer divides the semiconductor layer to allow a center position of a continuous region of the semiconductor layer or a center position of a region that divides the semiconductor layer to correspond to a position of an optical center of the sensor pixel, in at least one direction on a plane of the sensor pixel perpendicular to an optical axis direction.

Provided are an information processing device, an information processing method, and an information processing program capable of reducing a processing load of convolution processing in a convolutional neural network (CNN). An information processing device (1) according to the present disclosure includes a setting unit (51) and a control unit (52). The setting unit (51) sets exposure time of each of imaging pixels in an imaging unit (2), which includes a plurality of imaging pixels arrayed two-dimensionally, to exposure time corresponding to a convolution coefficient of a first layer of a CNN. The control unit (52) causes transfer of signal charges from imaging pixels, which have been exposed, to a floating diffusion (FD), thereby performing convolution processing.

An image sensor and a method of operating the same are provided. The image sensor includes a semiconductor substrate of a first conductivity type; a photoelectric conversion region provided in the semiconductor substrate and doped to have a second conductivity type; a first floating diffusion region provided to receive photocharges accumulated in the photoelectric conversion region; a transfer gate electrode disposed between and connected to the first floating diffusion region and the photoelectric conversion region; a dual conversion gain transistor disposed between and connected to the first floating diffusion region and a second floating diffusion region; and a reset transistor disposed between and connected to the second floating diffusion region and a pixel power voltage region, wherein a channel region of the reset transistor has a potential gradient increasing in a direction from the second floating diffusion region toward the pixel power voltage region.