A solid-state imaging device includes a plurality of pixel cells, each of the pixel cells including a light receiving element, a floating diffusion, a first source follower circuit, and a second source follower circuit. The plurality of pixel cells are connected to an output signal line. The light receiving element photoelectrically converts incident light, and stores a signal charge. The floating diffusion converts the signal charge read out of the light receiving element into a signal voltage. The first source follower circuit is connected to the floating diffusion, and outputs an output voltage corresponding to the signal voltage. The second source follower circuit is connected in series with the first source follower circuit, and outputs a pixel signal corresponding to the output voltage.

To make it possible to reduce power consumption in a charge pump that supplies driving power to a pixel array. An imaging element (4) according to an embodiment includes: an imaging unit (100) in which pixels (10) including a light receiving element are arrayed, a drive unit (112) that generates a drive signal for driving the pixels, a charge pump circuit (122) that generates electric power for driving the drive unit, and a control unit (120) that controls, according to operation of the imaging unit, a driving capability of the charge pump circuit to drive the drive unit.

It is an object to provide a solid-state imaging apparatus and a distance measurement system that can detect high-frequency pulsed light. The solid-state imaging apparatus includes a plurality of pixels, a drive section, and a time measurement section. Each of the plurality of pixels has a light-receiving element that converts received light into an electric signal. The drive section drives the plurality of pixels by shifting operation timings of the light-receiving elements. The time measurement section is provided such that the electric signal is input from each of the plurality of pixels and measures the time until light emitted from a light source is reflected by a subject and received by the light-receiving element on the basis of the input of the electric signal.

An imaging device includes an image sensing device, a private key generation unit, and an image encryption unit. The image sensing device includes an image generator configured to generate image data acquired by capturing as image, and a physical unclonable function (PUF) generator configured to generate physical unclonable function (PUF) data including information about at least one fixed pattern noise (FPN) data value and at least one random telegraph noise (RTN) data value. The private key (KEY) generation unit generates a private key based on the at least one FPN data value and the at least one RTN data value that are acquired from the PUF data. The image encryption unit encrypts the image data using the private key. A first transistor included in the PUF generator exhibits different properties from a second transistor that is included in the image generator and corresponds to the first transistor.

An imaging system includes a camera unit and a main body. A clock detection circuit is configured to detect a first clock signal of the camera unit from first digital data transmitted from the camera unit. A phase comparator is configured to generate second digital data that represent a difference between a phase of the first clock signal and a phase of a second clock signal of the main body. A second communicator is configured to perform communication in a second direction in which the second digital data are transmitted to the camera unit in a blanking period. A first clock generation circuit is configured to generate the first clock signal synchronized with the second clock signal on the basis of the second digital data.

A solid-state imaging apparatus according to an embodiment of the present disclosure includes a photoelectric transducer, a transfer transistor, a floating diffusion, a reset transistor, an amplifier transistor, and a selection transistor. The reset transistor includes a gate insulating film formed thinner than the gate insulating film of the transfer transistor.

An image sensor includes a plurality of pixels and photo gate controller circuitry. Each pixel may transmit a pixel signal, corresponding to a photoelectric signal, in response to a photo gate signal in a frame. The photo gate controller circuitry may generate photo gate signals and transmit photo gate signals to the pixels. The photo gate controller circuitry includes a first delay circuit configured to transmit first delay clock signals each being delayed with respect to a reference clock signal by a certain amount of time and a second delay circuit configured to transmit second delay clock signals each being delayed with respect to the reference clock signal by a certain amount of time. The pixels are each configured to selectively receive signals, as the photo gate signals, among the delay clock signals output from the first delay circuit and the delay clock signals output from the second delay circuit.

A timing of the readout from an imaging circuit is controlled from the outside of the imaging circuit. An exposure control signal receiving section is configured to receive, from outside, an exposure control signal that controls a timing at which plural pixels are exposed. A control signal receiving section is configured to receive, from the outside, a readout control signal that controls a timing at which the plural pixels are read out. A vertical driving control signal generating section is configured to generate, on the basis of the exposure control signal and the readout control signal, a vertical driving control signal that generates a control signal for exposure and readout with respect to each of pixel columns of a pixel section. A vertical driving circuit is configured to drive and control each of the pixel columns according to the vertical driving control signal.

An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.

An image sensor supporting a full resolution mode and a crop mode, the image sensor including: a pixel array including a plurality of pixels configured to generate a pixel signal by sensing an object; an analog-to-digital converter configured to convert the pixel signal into a digital signal and including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller including: a first transistor configured to activate all of the plurality of metal lines based on a first control signal; and a second transistor configured to activate a first metal line for the crop mode among the plurality of metal lines based on a second control signal.