In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

The present technology relates to a signal processing device and method, and a program that enable easier and more accurate failure detection. The signal processing device includes: an addition unit that adds test data for failure detection to valid data on which predetermined processing is to be performed, two or more samples processed in parallel in different paths having a same sample value in the test data; and a signal processing unit that performs the predetermined processing on the valid data and the test data that has been added to the valid data by a plurality of the paths. The present technology can be applied to in-car cameras.

To improve the correction accuracy in a solid-state image sensor that performs dark current correction. A solid-state image sensor includes a bias voltage supply unit and a signal processing unit. The bias voltage supply unit supplies a bias voltage of a predetermined value to a light-shielded pixel impervious to light in a period in which a light-shielded pixel signal is output from the light-shielded pixel, and supplies a bias voltage of a value different from the predetermined value to a photosensitive pixel not impervious to light in a period in which a photosensitive pixel signal is output from the photosensitive pixel. The signal processing unit executes processing of removing dark current noise from the photosensitive pixel signal using the light-shielded pixel signal.

An imaging device includes a controller and a generator. The controller controls an imaging unit on the basis of a command and data received from a host in accordance with an I2C/I3C communication protocol. The generator generates a second control signal indicating whether or not to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) on the basis of a first control signal received from the host via a first route different from the I2C/I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C/I3C communication protocol.

A transfer control device includes a difference identifying section which identifies, for a first and second images sequentially captured by synchronous scanning, a difference region of the second image, on the basis of an event signal indicating a change in intensity of light generated in one or a plurality of pixels of each of the first and second images during a time period from capturing of the first image to capturing of the second image; and a transfer control section which executes data transfer different between the difference region and regions other than the difference region, for the second image.

An information processing apparatus including a specification section specifying, from among a plurality of blocks that are set by dividing pixels included in at least a partial region of a pixel region having a plurality of pixels arrayed therein and each of which includes at least one or more of the pixels, at least one or more of the blocks, and a generation section generating a unique value based on pixel values of the pixels included in the specified blocks.

An image sensing device is provided to comprise: a pixel array of pixels that are operable to sense light to produce pixel signals and are operable to operate in one of a plurality of modes in sensing of light, wherein a first pixel of the pixel array is controlled to operate in a mode selected from the plurality of modes and configured to output a pixel signal in response to light incident onto the first pixel; and an analog-to-digital converter (ADC) coupled to the pixel array to receive the pixel signal from the first pixel and configured to set, based on the mode selected for the first pixel in generating the pixel signal, an input range indicating a voltage range of the pixel signal and perform an analog to digital conversion of the pixel signal generated by the first pixel to produce pixel data representing the pixel signal based on the input range of the analog-to-digital converter (ADC).

An image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.

Disclosed is an image adjustment apparatus including a receiver which is configured to receive a first input image of an object which is time-synchronously captured and a second input image in which a motion event of the object is sensed time-asynchronously, and an adjuster which is configured to adjust the first input image and the second input image.

An imaging device includes an image sensing circuitry configured to receive image signals from pixels, to convert the received image signals into image data, and to output the image data. The imaging device includes a digital processing circuitry configured to process image data in synchronization with a digital clock. The digital processing circuitry includes a digital clock generator configured to generate the digital clock. The digital clock generator is configured to scatter the digital clock, in response to the image sensing circuitry converting the image signals into the image data.