Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Methods and systems to construct models to transform weather information of one source to be statistically consistent with weather information of another source (i.e., to compensate for statistical differences/bias between the sources), without necessarily having to determine or compute the actual bias.

Disclosed is a system, computer program product, and method for performing logic, physical synthesis, and post-route optimization. The method begins with identifying a plurality of groups of paths in a circuit by a unique criteria. The unique criteria is any one of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof. An optimization process is performed on the design and is repeated until the cumulative histogram corresponds to the reference histogram within a threshold. The histogram optimization on the group of paths to make the cumulative histogram correspond to the reference cumulative histogram can be adjusted to account for timing, power, yield, or a combination thereof. After a first group of paths has been optimized, the process can be repeated for other groups of paths. The histogram optimization performed on each group of paths is merged into overall histogram optimization design.

An apparatus is provided for analysis of a leading edge rib of a fixed leading edge section of an aircraft wing. The apparatus may identify geometric or inertial properties of a plurality of stiffeners of the rib, and based thereon perform an analysis to predict a failure rate of the leading edge rib under an external load. From the failure rate, the apparatus may determine a structural integrity of the leading edge rib under the external load. Performing the analysis may include importing a plurality of section cuts into a finite element model of the rib and thereby identifying nodes proximate the section cuts. Under an external load, internal load distributions may be extracted from elements proximate the nodes and elements, and the failure rate of the leading edge rib under the external load may be predicted based on the internal load distributions of the elements.

A mechanism is described for facilitating smart crowd-sourced automatic indoor discovery and mapping according to one embodiment. A method of embodiments, as described herein, includes collecting data relating to a facility, where the data is based on one or more of movement data, contextual data, and observation data relating to at least one of an indoor space and one or more users of the indoor space. The method may further include generating one or more dynamic profiles of the indoor space and the occupants, and building a map of the indoor space based on the one or more dynamic profiles.

Methods and systems for timing analysis and optimization of asynchronous circuit designs are disclosed. Registration stages are placed between combinational logic circuits. For timing purposes, the registration stages are modified to have a duplicate set of pins. New paths are formed in the circuit for the purposes of timing analysis. The paths are analyzable by timing tools. Once the timing analysis is complete, the paths are reverted to original paths, and new devices are selected for the circuit design based on results of the timing analysis. An updated design is sent for manufacture, based on the timing analysis and optimization of the asynchronous circuit.

Aspects of the invention include global optimization of networks of locally fitted objects. An electronic representation of a network of intelligent objects is received. The network includes a plurality of intelligent objects and a plurality of gaps greater than a threshold between at least three of the intelligent objects. An aligned model of the network is created where all gaps in the aligned model of the network are less than the threshold. The creating includes optimizing a first plurality of the intelligent objects towards an axis of a second plurality of intelligent objects, and aligning the second plurality of intelligent objects towards the first plurality of intelligent objects. The optimizing and aligning are iteratively performed until a stopping condition is met. The aligned model of the network is output.

A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

A method is provided to design a filter. In the method, a difference between a high frequency to be blocked and a resonance frequency of a distributed constant type reference filter is obtained, the reference filter including a reference coil having windings wound at a plurality of pitches having the same length in an axial direction and a capacitor connected in parallel to the reference coil. When the difference is greater than the predetermined value, a split position in the reference coil where the reference coil is divided into a first coil element and a second coil element connected in series and a split distance between the first coil element and the second coil element to reduce the first difference.

A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.