Patent classifications
G06F17/50
Method of manufacturing semiconductor device
A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.
Removing sharp cusps from 3D shapes for additive manufacturing
A method for processing a three-dimensional (3D) mesh model includes receiving a 3D mesh model. One or more regions including a potential sharp cusp are automatically detected. The automatically detected one or more regions are displayed to a user and an active region of the 3D mesh model is defined by the user. Sphere fitting and Laplacian smoothing are applied to the designated active region to remove a sharp cusp therefrom and to obtain a modified 3D mesh model.
4D vizualization of building design and construction modeling with photographs
A system and method are disclosed for, using structure-from-motion techniques, projecting a building information model (BIM) into images from photographs taken of a construction site, to generate a 3D point cloud model using the BIM and, when combined with scheduling constraints, facilitates 4D visualizations and progress monitoring. One of the images acts as an anchor image. Indications are received of first points in the anchor image that correspond to second points in the BIM. Calibration information for an anchor camera is calculated based on the indications and on metadata extracted from the anchor image, to register the anchor image in relation to the BIM. A homography transformation is determined between the images and the anchor camera using the calibration information, to register the rest of the images with the BIM, where some of those images are taken from different cameras and from different angles to the construction site.
System and method for efficient statistical timing analysis of cycle time independent tests
A system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.
Computer-aided modeling
A modeling application is provided with at least one repetition object type for creating at least one repetition instance of at least one repetitive article in a model, wherein the repetition object type is provided to be used for creating one or more repetition objects, a repetition object comprising at least one finite geometry definition surface definition that defines a geometry definition surface and its location in the model, and guide information. One or more repetition instances of a repetitive article are determined using of the at least one geometry definition surface and the guide information.
Systems and methods for gas turbine operational impact modeling using statistical and physics-based methodologies
Systems and methods for gas turbine operational impact modeling using statistical and physics-based methodologies are disclosed. According to one embodiment of the disclosure, a method can include receiving, by one or more processors, operational conditions data associated with a hardware component of a gas turbine; based at least in part on the operational variation data, applying, by one or more processors, statistical methods to establish an operational profile of the hardware component; receiving, by one or more processors, operating parameters and operational conditions data associated with the hardware component; based at least in part on the operating parameters and the operational conditions data, applying, by one or more processors, physics-based methods to establish an operational impact factor of the hardware component; and based at least in part on the operational profile and the operational impact factor determining, by one or more processors, a probability of a failure of the hardware component within a time period.
Atomic scale grid for modeling semiconductor structures and fabrication processes
Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An iterating module iterates through the time steps to determine values for physical quantities of the body at the end of the simulation period. Preferably one particle of the body is assigned to each node of the grid. For moving boundary processes, boundary movement can be represented simply by changing the particle type assigned to various nodes of the grid as the boundary advances.
Multi-objective design optimization using adaptive classification
Definition of a design space and an objective space for conducting multi-objective design optimization of a product is received in a computer system having a design optimization application module installed thereon. Design space is defined by design variables while objective space is defined by design objectives. First set of designs in the design space is selected. Each of the first set is evaluated in the objective space for non-dominance. Design space is partitioned into first and second regions using a multi-dimensional space division scheme (e.g., SVM). The first region is part of the design space containing all of the non-dominated design alternatives while the second region contains remaining of the design space. Second set of designs is selected within the first region. Each of the second set and existing non-dominated design alternatives are evaluated for non-dominance. Multi-objective optimization repeats the partition and evaluation until an end condition is reached.
Transistor plasma charging eliminator
An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.
Method for producing an integrated circuit package and apparatus produced thereby
A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.