A semiconductor device including a transistor having a minute size is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes first to third conductive layers, an insulating layer, and first and second semiconductor layers. The second conductive layer over the first conductive layer includes an opening overlapping with the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer and a top surface and a side surface of the second conductive layer. The second semiconductor layer is in contact with a top surface of the first semiconductor layer. The insulating layer is in contact with a top surface of the second semiconductor layer. The third conductive layer overlaps with the first and second semiconductor layers in the opening. The second transistor includes the insulating layer, a third semiconductor layer, and fourth to sixth conductive layers. The fourth and fifth conductive layers are in contact with different top surfaces of the third semiconductor layer. Between the fourth semiconductor layer and the fifth semiconductor layer, the insulating layer is in contact with a top surface of the third semiconductor layer. The sixth conductive layer is in contact with a top surface of the insulating layer. The first and second semiconductor layers contain different materials. The second and third semiconductor layer contain the same material.

A semiconductor device includes: a first capacitor element that includes a first electrode, a second electrode, and a dielectric layer positioned between the first electrode and the second electrode; and a second capacitor element that includes a third electrode and an insulating layer positioned between the second electrode and the third electrode. The first capacitor element includes at least one first trench portion.

A method of manufacturing a semiconductor device includes: forming a silicon nitride film over a first conductive film; widening the silicon nitride film; after widening the silicon nitride film, forming a first film containing carbon over the silicon nitride film and a second conductive film; forming a first silicon oxide film surrounding the first film over the silicon nitride film and the second conductive film; removing the first film to form, in the first silicon oxide film, a first opening that exposes at least a part of the silicon nitride film and at least a part of the second conductive film; and forming a third conductive film on and in contact with the second conductive film in the first opening.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:

Mc/+Mr

Mr{square root over (1/2ft)}[Math. 1] where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, denotes a resistivity of the resistor, denotes a MOS capacitance rate of the MOS capacitor, and denotes a MOM capacitance rate of the MOM capacitor.

The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.

A semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and first to fourth wirings. The first transistor includes a first gate and a second gate, and one of a source and a drain of the first transistor is connected to the first wiring and the second gate, and the other of the source and the drain is connected to one of a source and a drain of the second transistor and one electrode of the capacitor. A gate of the second transistor is connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring. The first wiring is supplied with a first potential, and the second wiring is supplied with a second potential and a third potential alternately. The third wiring is connected to the first gate and supplied with a first signal. The fourth wiring is connected to the gate of the second transistor and supplied with a second signal obtained by inverting the first signal.

The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.

Provided is a solid-state imaging device that includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a photoelectric conversion section and an electric charge accumulation section for each of pixels. The electric charge accumulation section accumulates signal charge generated in the photoelectric conversion section. The second semiconductor layer includes a pixel transistor that reads out the signal charge of the electric charge accumulation section. This solid-state imaging device includes a pixel separation section and a shared coupling section. The pixel separation section is provided in the first semiconductor layer. The pixel separation section partitions a plurality of the pixels from each other. The shared coupling section is provided between the second semiconductor layer and the first semiconductor layer. The shared coupling section is provided across the pixel separation section.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a base substrate including a trench, where the trench includes a gate structure whose top surface is lower than a top surface of the trench; first etch stop layers, where the first etch stop layers cover the top surface of the gate structure, part of a side wall of the trench, and an upper surface of the base substrate; an enclosed isolation structure positioned between the first etch stop layers in the trench, where the enclosed isolation structure at least plugs an opening of the trench; and an air gap positioned between the first etch stop layer and the enclosed isolation structure, where the air gap at least includes a transverse portion, and a bottom of the enclosed isolation structure is positioned on the transverse portion.

A memory device that can be miniaturized or highly integrated is provided. The memory device includes: a first insulator over a substrate; an oxide semiconductor covering the first insulator; a first conductor and a second conductor over the oxide semiconductor; a second insulator over the first conductor; a third insulator over the second conductor; a third conductor over the second insulator; a fourth conductor over the third insulator; a fourth insulator that is placed over the third conductor and the fourth conductor and includes a first opening overlapping with a region between the first conductor, the second insulator, and the third conductor and the second conductor, the third insulator, and the fourth conductor; a fifth insulator placed in the first opening and over the oxide semiconductor; a fifth conductor placed in the first opening and over the fifth insulator; a sixth conductor placed in a second opening formed in the fourth insulator and being in contact with the top surface of the third conductor; and a seventh conductor placed in a third opening formed in the fourth insulator, the third insulator, and the fourth conductor and being in contact with the top surface of the second conductor. The height of the first insulator is larger than the width of the first insulator.