A semiconductor device that occupies a small area is provided. The semiconductor device includes a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer over the second conductive layer, a semiconductor layer and a third conductive layer over the first insulating layer, a second insulating layer over the semiconductor layer and the third conductive layer, and a fourth conductive layer over the second insulating layer; at least part of the second conductive layer is in contact with a top surface of the first conductive layer; the semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second conductive layer, the third conductive layer, and a side surface of the first insulating layer; and the fourth conductive layer overlaps with the semiconductor layer with the second insulating layer therebetween.

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

A semiconductor device includes transistors formed in a substrate. The transistors form at least a first cell functioning under a first power supply voltage, a second cell functioning under a second power supply voltage that is different from the first power supply voltage, and a third cell functioning under both the first power supply voltage and the second power supply voltage. The semiconductor device also includes a frontside power rail disposed on a frontside of the substrate and a backside power rail disposed on a backside of the substrate. The frontside power rail provides the first power supply voltage to the first cell and the third cell. The backside power rail provides the second power supply voltage to the second cell and the third cell.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. Both the transistor portion and the diode portion include a base region of a second conductivity type on a front surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the front surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.

An equalization circuit structure includes a semiconductor substrate including an equalization active region; a gate layer including a gate pattern and a power supply line, wherein the gate pattern is disposed on the equalization active region and configured for forming a transistor unit with the equalization active region, and the power supply line electrically connects the equalization active region with an external power supply and is configured for supplying power to the transistor unit.

A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor, a second conductor, and a third insulator over the oxide semiconductor, a second insulator over the first insulator, the first conductor, and the second conductor, and a third conductor over the third insulator. The oxide semiconductor includes a first region overlapping with the first conductor, a second region overlapping with the second conductor, and a third region positioned between the first region and the second region. The second insulator includes an opening portion in a region overlapping with the third region, and the third insulator and the third conductor are provided in the opening portion. The first region and the second region are in contact with the first insulator and the second insulator, and the third region is in contact with the first insulator and the third insulator. The first insulator and the second insulator contain silicon and nitrogen.

A semiconductor device that has both high performance and high productivity is provided. The semiconductor device includes a first transistor and a second transistor over a substrate. The first transistor includes a first conductive layer, a first insulating layer, and a second conductive layer in this order, and includes a first semiconductor layer, a second insulating layer, and a third conductive layer in this order over the first conductive layer in an opening provided in the first insulating layer and the second conductive layer. The second transistor includes the first insulating layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, the second insulating layer, and a sixth conductive layer in this order, and the second semiconductor layer includes a region in contact with the second insulating layer and a region overlapping with the second insulating layer with the fourth conductive layer or the fifth conductive layer therebetween. The second conductive layer, the fourth conductive layer, and the fifth conductive layer can be formed from the same film.

A semiconductor device with a high on-state current is provided. An oxide film; a source electrode and a drain electrode over the oxide film; an interlayer insulating film covers the oxide film, the source electrode, and the drain electrode; a gate insulating film over the oxide film; a barrier insulating film over the oxide film; and a gate electrode over the gate insulating film are included. The barrier insulating film is between the source electrode and the gate insulating film and between the drain electrode and the gate electrode. An opening is formed in the interlayer insulating film so as to overlap with a region between the source electrode and the drain electrode. The barrier insulating film, the gate insulating film, and the gate electrode are in the opening. Above the barrier insulating film, the gate insulating film is in contact with the interlayer insulating film.