A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided over the first insulating layer. The first insulating layer and the second conductive layer include an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second semiconductor layer is provided over the first semiconductor layer. The third semiconductor layer is provided over the second semiconductor layer. The first semiconductor layer contains a first material. The second semiconductor layer contains a second material. The third semiconductor layer contains a third material. A band gap of the first material is larger than a band gap of the second material. A band gap of the third material is larger than the band gap of the second material.

A novel metal oxide and a formation method thereof are provided. The metal oxide includes a first crystal, a second crystal, and a region positioned between the first crystal and the second crystal. The c-axis of the first crystal is substantially parallel to the c-axis of the second crystal. The crystallinity of the region is lower than those of the first crystal and the second crystal. The width of the region in the direction perpendicular to the c-axis of the first crystal is greater than 0 nm and less than 1.5 nm. The first crystal and the second crystal each have a layered crystal structure.

A semiconductor device with a novel configuration is provided. The semiconductor device includes a first element layer including a bit line driver circuit; a second element layer including a first switch circuit, a first memory cell, and a first wiring provided between the first switch circuit and the first memory cell; and a third element layer including a second switch circuit, a second memory cell, and a second wiring provided between the second switch circuit and the second memory cell. The first switch circuit has a function of establishing a non-conduction state between the first wiring and a third wiring in data write operation or read operation of the second memory cell. The second switch circuit has a function of establishing a non-conduction state between the second wiring and the third wiring in data write operation or read operation of the first memory cell.

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. In the semiconductor device, an insulating layer functioning as a first spacer is provided between a lower electrode that is one of a source electrode and a drain electrode of a transistor and an upper electrode that is the other, and an insulating layer functioning as a second spacer is provided over the upper electrode. The first spacer, the upper electrode, and the second spacer are provided with a first opening portion reaching the lower electrode. Inside the first opening portion, a semiconductor layer where a channel is formed is provided to connect the lower electrode and the upper electrode. Inside the first opening portion, a gate insulating layer and a gate electrode are provided to overlap with the semiconductor layer. An interlayer insulating layer including a second opening portion reaching the gate electrode is provided over the second spacer, the semiconductor layer, the gate insulating layer, and the gate electrode. The gate electrode includes a region in contact with a wiring over the interlayer insulating layer inside the second opening portion.

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is positioned above the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is positioned above the first insulating layer. The semiconductor layer is in contact with the second conductive layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is positioned above the third insulating layer and includes a second opening reaching the third insulating layer in a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.