The present disclosure relates to integrated circuits which include various structural elements. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate.

A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region.

A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

The present invention introduces the ASIC integrated MEMS device with exposed bond-pads from bottom attached ASIC and method for making the same. The ASIC integrated MEMS device with exposed bond-pads from bottom attached ASIC can be especially used for micromirror array MEMS devices. With the present invention and technology, individually controlling of thousands of micromirrors becomes possible and bring easier fabrication method. With the present invention and technology, individually controllable micromirror array can implement easier control method and more compact packing becomes feasible. With help of the present invention scheme, more complicated light modulating device scheme can be implemented with micromirror array or MEMS device with a large number of controlling channels. Scheme, apparatus, and method are disclosed in the present invention.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a metal oxide, a first conductor and a second conductor over the metal oxide, a first insulator over the first conductor and the second conductor, a second insulator over the first insulator, a third insulator that is between the first conductor and the second conductor and is over the metal oxide, a third conductor over the third insulator, a fourth conductor that is over the third conductor and is electrically connected to the third conductor, a fourth insulator over the fourth conductor, a fifth insulator over the fourth insulator, and a fifth conductor including a region overlapping with the fourth conductor. The metal oxide includes a first region that overlaps with the first conductor and extends in a first direction. In the first region, an end portion of the metal oxide is aligned with an end portion of the first conductor. The first direction is parallel to a direction in which the fifth conductor extends.

A semiconductor device including a transistor is provided. The transistor comprises a second conductive layer in contact with a top surface of a first conductive layer. A third conductive layer over the second conductive layer includes a second opening overlapping with a first opening of the second conductive layer. A first insulating layer is in contact with a sidewall of the first opening and a semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface of the third conductive layer. A second insulating layer is over the semiconductor layer, a fourth conductive layer is over the second insulating layer, and the first insulating layer includes a region interposed between the sidewall of the first opening and the semiconductor layer.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, a third insulator over the second insulator, a fourth insulator over the third insulator, and an opening region. The opening region includes the second insulator, the third insulator over the second insulator, and the fourth insulator over the third insulator. The third insulator includes an opening reaching the second insulator. The fourth insulator is in contact with a top surface of the second insulator inside the opening.

In a semiconductor integrated circuit device, first and second interconnects extending in the X direction are formed in a metal interconnect layer. The first and second interconnects are placed on the opposite sides of each resistor element in the X direction and connected to the resistor element. The first interconnect is connected to PAD, and a third interconnect is connected to VSS. In an ESD protection diode, an anode and a cathode are formed alternately in the Y direction. The resistor element and the first and second interconnects overlap the cathode of the ESD protection diode, and the third interconnect overlaps the anode of the ESD protection diode, in planar view.

A semiconductor device with high memory density and high reliability is provided. A first to a third layers are stacked in the semiconductor device. The first layer includes a delay signal generation circuit and a row circuit. The second layer includes a first delay addition circuit and a first memory cell, and the third layer includes a second delay addition circuit and a second memory cell. The delay signal generation circuit has a function of generating a first and a second delay signals representing a first and a second delay times, respectively, and supplying the first and the second delay signals to the first and the second delay addition circuits, respectively. The row circuit has a function of generating a row selection signal for selecting a first or a second memory cell performing reading operation and supplying it to the first or the second delay addition circuit. The first delay addition circuit has a function of supplying the row selection signal to the first memory cell after the first delay time elapses. The second delay addition circuit has a function of supplying the row selection signal to the second memory cell after the second delay time elapses. The first delay time is longer than the second delay time.

A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a second oxide provided over the first oxide and being in contact with the side surface of the first conductor and the side surface of the second conductor; a third oxide provided over the second oxide and including regions in contact with the side surface of the first insulator and the side surface of the second insulator; a third insulator over the third oxide; and a third conductor over the third insulator.