A harmonic termination circuit is integrated into an RF amplifier semiconductor structure. A MIMcap is formed on a grounded source finger of an RF transistor amplifier, and one or more bond wires connect the MIMcap to a gate or drain bond pad of the transistor. The bond wire has an inherent inductance, and together with the MIMcap forms a series LC resonant circuit connected in shunt configuration from the gate or drain bond pad to ground. The LC circuit is tuned to shunt the desired harmonic component to ground, such as by adjusting the length of the bond wire (e.g., by altering its height). Such adjustment can be made after fabrication of the integrated circuit die is complete, and can be changed without requiring re-fabrication. The harmonic termination circuit resides entirely within the amplifier area, and does not increase the size of the die.

A method and system of arranging patterns of a semiconductor device are provided. The method includes: generating a plurality of active region layout patterns; generating a plurality of gate region layout patterns; and generating a plurality of dummy gate region layout patterns, and generating a plurality of cut feature layout patterns. The plurality of active region layout patterns, the plurality of cut feature layout patterns, the plurality of gate region layout pattern, and the plurality of dummy gate region layout patterns exhibit a plurality of units repeating periodically along at least one of the first direction, the second direction, or both.

A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.

A semiconductor device includes: first fins (F-fins) and second fins (S-fin) arranged in a first row having a single-row height and that includes an alpha cell region and a beta cell region. The alpha cell region includes a first F-fin, a first S-fin and a first gate structure overlapping each of the first F-fin and the first S-fin. The first gate structure does not overlap top and bottom edges of the alpha cell region. The beta cell region includes second and third F-fins, second and third S-fins and a second gate structure overlapping each of the second F-fin and second S-fin and at least one of the third F-fin or the third S-fin. A top edge of the beta cell region being co-track aligned with the third F-fin. A bottom edge of the beta cell region being co-track aligned with the third S-fin.

Semiconductor die and methods for manufacturing the same are provided. In one example, a semiconductor wafer having a plurality of lateral semiconductor device units may be provided. One or more cut lines, which group the plurality of lateral semiconductor device units into a plurality of semiconductor die, may be determined, and the semiconductor wafer may be cut along the one or more cut lines. In some examples, semiconductor die cut from the semiconductor wafer may have the same or different sizes. In some examples, semiconductor die cut from the semiconductor wafer may have the same or different numbers of lateral semiconductor device units. In some examples, a semiconductor die cut from the semiconductor wafer may include one or more uncut scribe lines between each of a plurality of lateral semiconductor device units.

Transconductance (gm) of a field effect transistor is improved. A semiconductor device includes: a semiconductor portion having an island shape having an upper surface portion and a side surface portion; a field effect transistor having a gate electrode provided on the semiconductor portion with a gate insulating film interposed therebetween; an insulating layer covering the field effect transistor; and a contact electrode provided on the insulating layer to overlap the semiconductor portion outside the gate electrode in plan view. Then, the contact electrode is connected to the upper surface portion and the side surface portion of the semiconductor portion.

A novel display apparatus that is highly convenient, useful, or reliable is provided. The display apparatus includes a first pixel set, a second pixel set, a first conductive film, and a second conductive film; the first pixel set includes a first light-emitting device set and a first pixel circuit set; the first pixel circuit set includes a first group of pixel circuits; and the first group of pixel circuits include a first pixel circuit. The second pixel set includes a second light-emitting device set and a second pixel circuit set; the second light-emitting device set is electrically connected to the second pixel circuit set; the second pixel circuit set includes a second group of pixel circuits; and the second group of pixel circuits include a second pixel circuit. The first conductive film is electrically connected to the first group of pixel circuits and the second group of pixel circuits, and the second conductive film is electrically connected to the first pixel circuit and the second pixel circuit.

There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.

A display apparatus with a novel structure or a display system with a novel structure is provided. The display system includes a first display apparatus and a second display apparatus. The first display apparatus and the second display apparatus each have a wireless communication function. The second display apparatus includes a region having higher pixel density than the first display apparatus and has a function of displaying a screen of the first display apparatus or a part of the screen of the first display apparatus on the second display apparatus using the wireless communication function. A screen ratio of the second display apparatus is preferably 1:1, 4:3, or 16:9.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, a third insulator over the second insulator, a fourth insulator over the third insulator, and an opening region. The opening region includes the second insulator, the third insulator over the second insulator, and the fourth insulator over the third insulator. The third insulator includes an opening reaching the second insulator. The fourth insulator is in contact with a top surface of the second insulator inside the opening.