A crossbar switch has N input ports, M output ports, and a switching matrix with N×M crosspoints. In an embodiment, each crosspoint contains an internal queue (XQ), which can store one or more packets to be routed. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N×M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements a shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the row scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughput with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.

An optoelectronic switch comprising: a first plurality of detector remodulators (DRMs) (C3, D1), each DRM having an integer number M of optical inputs and an integer number N of optical outputs; a second plurality of DRMs (C7, D5), each DRM having N optical inputs and M optical outputs; a passive optical switch fabric (C4+C5+C6, D2+D3+D4) connecting the N optical outputs of each of the first plurality of DRMs with the N optical inputs of each of the second plurality of DRMs, the path of an optical signal through the optical switch fabric depending upon its wavelength; wherein each DRM (C3, D1) of the first plurality of DRMs is configured to act as a tunable wavelength converter to select the desired path of an optical signal through the optical switch fabric (C4+C5+C6, D2+D3+D4); and wherein each of the first plurality of DRMs (C3, D1) includes a concentrator, the concentrator configured to aggregate optical signals received from any of the M inputs of that DRM and to buffer them according to the one of the plurality of second DRMs (C7, D5) that includes their destination port.

A switching device includes a processor, an input buffer, an output buffer, and a Banyan switching architecture, where the processor is configured to convert an initial switching table to a non-congestion switching table and an order-adjustment table using a preset reordering algorithm; the input buffer is configured to save first period data that is from an input port; the processor is further configured to perform, using the non-congestion switching table, data switching on data in the first full-period data saved in the input buffer, to obtain second full-period data; the Banyan switching architecture is configured to perform synchronous data switching on the second full-period data; the output buffer is configured to save the second full-period data on which the synchronous data switching has been performed; the processor is further configured to adjust, using the order-adjustment table, a data order of the second period data.

System and method embodiments are provided for optical I/O arrays for wafer scale testing. A wafer includes a plurality of dies of PIC chips. Each die includes a plurality of first and second optical I/O elements each configured to couple to a testing probe array. A row of I/O elements includes alternating ones of the first and second optical I/O elements. Each die also includes a first waveguide and a second waveguide coupling a first one of the first and second optical I/O elements to a second one of the first and second optical I/O elements, respectively. The first and second optical I/O elements configured such that the testing probe array couples to at least some of the first optical I/O elements from a first side of the PIC chip and couples to at least some of the second optical I/O elements from a second side of the PIC chip.

As part of starting a system including a system-on-a-chip (SoC) device fro a mode in which power is removed from the system, the SoC device determines, based on the metadata, whether to resume the system to a prior system state. In response to the metadata indicating that the system is to be resumed to the prior system state, the system is resumed to the prior system state using system state information stored in the on-chip non-volatile memory.

The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.

A transition protocol is provided herein in which a first rule set for routing packets received by a group of switches during a first time period is to be updated to a second rule set. During a transition period, at least some switches in the group of switches route packets to a controller, while other switches in the group of switches route packets to a next hop that is unchanged by the change in the rule set. The controller forwards packets that are received from at least some of the switches in the group to a destination node each of the packets, as determined from the updated rule set.

A method and a multi-switch architecture include learning a media access control (MAC) address at a first switch in a multi-switch architecture; storing the MAC address in a forwarding database of the first switch; transmitting a data frame to one or more switches in the multi-switch architecture via inter-switch connectivity between the first switch and the one or more switches, wherein the data frame is created to enable the one or more switches to learn the MAC address therefrom; learning the MAC address from the data frame at the one or more switches; and storing the MAC address in a forwarding database for each of the one or more switches. This further includes transmitting the data frame via ports and queues in the inter-switch connectivity that are separate from ports and queues in a data path between the first switch and the one or more switches to avoid data path interference.

An electronic device comprised of an HDMI Matrix/Switcher IC and IP Extension Processor. The invention will carry out this process by utilizing an HDMI matrix/switcher IC to control the flow of the HDMI signals to and from the IP processor. This allows one or more sources to be selected as the input to the IP processor or received content from the IP processor to be routed through the input of the HDMI matrix/switcher to an HDMI output of the HDMI matrix/switcher. This topology when configured as a transmitter can send the HDMI source over IP and can select which input is to be sent to the local HDMI output(s) of the unit. When configured as a receiver the IP content being received can be sent to the HDMI output(s) of the unit or same unit can select from one of the other HDMI input(s). The main intent of the invention would be to eliminate the need for 2 different products to achieve the end to end results and it allows for local switching and loop-out capabilities of the HDMI sources.

Various embodiments implement a set of low overhead mechanisms to enable on-demand routing protocols. The on-demand protocols use route accumulation during discovery floods to discover when better paths have become available even if the paths that the protocols are currently using are not broken. In other words, the mechanisms (or “Route Optimizations”) enable improvements to routes even while functioning routes are available. The Route Optimization mechanisms enable nodes in the network that passively learn routing information to notify nodes that need to know of changes in the routing information when the changes are important. Learning routing information on up-to-date paths and determining nodes that would benefit from the information is performed, in some embodiments, without any explicit control packet exchange. One of the Route Optimization mechanisms includes communicating information describing an improved route from a node where the improved route diverges from a less nearly optimal route.