A semiconductor storage device includes a memory cell including a switching element and a variable resistance element, and a circuit for switching the memory cell ON, performing a first read operation on the memory cell, generating a first voltage based on the first read operation, switching the memory cell ON after first data is written to the memory cell, performing a second read operation while the memory cell is maintained to be ON when the first data is stored in the memory cell during the first read operation, performing the second read operation after the memory cell transitions from ON to OFF at least once when second data is stored in the memory cell during the first read operation, generating a second voltage based on the second read operation, and determining the data stored in the memory cell during the first read operation based on the first and second voltages.

An ultra-fast magnetic random access memory (MRAM) comprises a three terminal composite SOT magnetic tunneling junction (CSOT-MTJ) element including a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer.

IC devices with stacked backend memory with resistive switching devices are disclosed. An example IC device includes a support structure, a frontend layer with a plurality of frontend devices, and a backend layer with a plurality of resistive switching devices, the resistive switching devices being, e.g., part of memory cells of stacked backend memory. For example, the backend layer may implement stacked arrays of 1T-1RSD memory cells, with resistive switching devices coupled to some S/D regions of access transistors of the memory cells. Such memory cells may be used to implement stacked eMRAM or eRRAM, with access transistors being TFTs. Stacked TFT-based eMRAM or eRRAM as described herein may help increase density of MRAM or RRAM cells, hide the peripheral circuits that control the memory operation below the memory arrays, and address the scaling challenge of some conventional memory technologies.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an interconnect structure and an electrode layer formed over the interconnect structure. The semiconductor structure also includes a gate dielectric layer formed over the electrode layer and an oxide semiconductor layer formed over the gate dielectric layer. The semiconductor structure also includes an indium-containing feature covering a surface of the oxide semiconductor layer and a source/drain contact formed over the indium-containing feature.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.

A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer; and patterning the second SOT layer and the passivation layer.

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

A semiconductor device including a magnetic tunnel junction stack, a metallic hard mask aligned above the magnetic tunnel junction stack and an air gap surrounding the metallic hard mask. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, forming barrier on vertical side surfaces of the dielectric, and removing the dielectric between the metallic hard mask and the barrier. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, selectively removing a portion of the dielectric surrounding the metallic hard mark.