H01L27/22

LAYERED STRUCTURE, MAGNETORESISTIVE DEVICE USING THE SAME, AND METHOD OF FABRICATING LAYERED STRUCTURE
20220384711 · 2022-12-01 ·

A layered structure which achieves both high spin polarization and low electrical resistance is provided. The layered structure includes a Heusler alloy, and graphene that is in direct contact with the surface of the Heusler alloy. Such a layered structure is fabricated by forming a thin film of the Heusler alloy over a substrate under vacuum, and growing graphene on the surface of the thin film of the Heusler alloy while maintaining the vacuum.

SELECTIVELY BIASING MAGNETORESISTIVE RANDOM-ACCESS MEMORY CELLS

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

SPIN-ORBIT TORQUE (SOT) MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH LOW RESISTIVITY SPIN HALL EFFECT (SHE) WRITE LINE

Embodiments of the invention include a method for fabricating a magnetoresistive random-access memory (MRAM) structure and the resulting structure. A first type of metal is formed on an interlayer dielectric layer with a plurality of embedded contacts, where the first type of metal exhibits spin Hall effect (SHE) properties. At least one spin-orbit torque (SOT) MRAM cell is formed on the first type of metal. One or more recesses surrounding the at least one SOT-MRAM cell are created by recessing exposed portions of the first type of metal. A second type of metal is formed in the one or more recesses, where the second type of metal has lower resistivity than the first type of metal.

CORE MAGNETIZATION REVERSAL METHOD OF SKYRMION AND DATA STORAGE DEVICE USING THE METHOD

A core magnetization reversal method includes transforming the first magnetic skyrmion into a skyrmionium by applying a first alternating current (AC) magnetic field to the first magnetic skyrmion, and then transforming the skyrmionium into a second magnetic skyrmion by applying a second AC magnetic field to the skyrmionium. The first magnetic skyrmion may be formed on a hemispherical shell, which may be formed by (i) preparing a membrane having a plurality of protrusions, and (ii) stacking, on the membrane, a first layer including at least one of platinum (Pt), nickel (Ni), and palladium (Pd), and a second layer including a ferromagnetic material. The first and second AC magnetic fields may have different frequencies.

MAGNETIC MEMORY DEVICE

Disclosed is a magnetic memory device including a pinned magnetic pattern and a free magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a top electrode on the free magnetic pattern, and a capping pattern between the free magnetic pattern and the top electrode. The capping pattern includes a lower capping pattern, an upper capping pattern between the lower capping pattern and the top electrode, a first non-magnetic pattern between the lower capping pattern and the upper capping pattern, and a second non-magnetic pattern between the first non-magnetic pattern and the upper capping pattern. Each of the lower capping pattern and the upper capping pattern includes a non-magnetic metal. The first non-magnetic pattern and the second non-magnetic pattern include different metals from each other.

ALIGNMENT MARK FOR MRAM DEVICE AND METHOD

Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.

MRAM CIRCUIT STRUCTURE AND LAYOUT STRUCTURE

A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

Cross-Point MRAM Including Self-Compliance Selector
20220383920 · 2022-12-01 ·

The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

MRAM-BASED CHIP IDENTIFICATION WITH FREE RANDOM PROGRAMMING

A magnetoresistive random access memory (MRAM) device having chip identification using normal operating voltages is provided. No dedicated programming is needed. Instead, programming of the MRAM device is free and random and is a result of providing a magnetic via structure sufficiently close to the magnetic free layer of the magnetic junction tunnel (MTJ) structure such that the magnetic via structure projects a magnetic field that interacts with the magnetic free layer and aligns the magnetization of the magnetic free layer with the magnetization of the magnetic via structure. Thus, the orientation of the magnetization of both the magnetic via structure and the magnetic free layer are aligned in a same direction. The magnetization of the magnetic via structure can thus be used as a physical unclonable function and the MTJ structure can be used to read out this information.

MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.