A magnetic domain wall movement element includes a magnetic recording layer which includes a ferromagnetic material; a non-magnetic layer which is laminated on the magnetic recording layer; and a magnetization reference layer which is laminated on the non-magnetic layer, in which the magnetic recording layer has a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in order from the non-magnetic layer, a magnetization of the first ferromagnetic layer and a magnetization of the second ferromagnetic layer are antiferromagnetically coupled, and an electrical resistivity of the first ferromagnetic layer is higher than the electrical resistivity of the second ferromagnetic layer.

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a semiconducting metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The semiconducting metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

A method of forming a semiconductor memory device is disclosed. A top electrode layer is formed on the MTJ stack layer. A patterned buffer layer is formed to cover only the logic circuit region. A hard mask layer is formed on the top electrode layer and the patterned buffer layer. A patterned resist layer is formed on the hard mask layer. A first etching process is performed to etch the hard mask layer and the top electrode layer not covered by the patterned resist layer in the memory region and the hard mask layer, the patterned buffer layer and the top electrode layer in the logic circuit region, thereby forming a top electrode on the MTJ stack layer in the memory region and a remaining top electrode layer covering only the logic circuit region on the MTJ stack layer.

The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating two magnetic free layers separated by a perpendicular enhancement layer (PEL) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic reference layer structure includes first, second, and third magnetic reference layers separated by two PELs and having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.

A magnetic structure capable of field-free spin-orbit torque switching includes a spin-orbit coupling base layer and a ferromagnetic layer formed thereon. The spin-orbit coupling base layer is made from a particular crystal material. The ferromagnetic layer has magnetization perpendicular to a plane coupled to the spin-orbit coupling base layer, and is made from a particular ferromagnetic material with perpendicular magnetic anisotropy. The perpendicular magnetization of the ferromagnetic layer is switchable by an in plane current applied to the spin-orbit coupling base layer without application of an external magnetic field. A memory device and a production method regarding the magnetic structure are also provided.

An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.

Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. The structure includes a non-volatile memory element having a magnetic-tunneling-junction layer stack. The magnetic-tunneling-junction layer stack has a fixed layer that includes a synthetic antiferromagnetic layer. The structure further includes a via positioned adjacent to the magnetic-tunneling-junction layer stack. The via is comprised of a magnetic material.