H01L43/04

SOI SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING AN SOI SEMICONDUCTOR STRUCTURE
20210366984 · 2021-11-25 · ·

An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

MAGNETIC MEMORY DEVICE
20210367142 · 2021-11-25 ·

A magnetic memory device including a lower electrode on a substrate; a conductive line on the lower electrode; and a magnetic tunnel junction pattern on the conductive line, wherein the conductive line includes a first conductive line adjacent to the magnetic tunnel junction pattern; a second conductive line between the lower electrode and the first conductive line; and a high resistance layer at least partially between the first conductive line and the second conductive line, a resistivity of the second conductive line is lower than a resistivity of the first conductive line, and a resistivity of the high resistance layer is higher than the resistivity of the first conductive line and higher than the resistivity of the second conductive line.

Magnetic Tunneling Junction with Synthetic Free Layer for SOT-MRAM
20210367143 · 2021-11-25 ·

A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

HALL INTEGRATED CIRCUIT AND CORRESPONDING METHOD OF MANUFACTURING OF A HALL INTEGRATED CIRCUIT USING WAFER STACKING

A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Image sensor incorporating an array of optically switchable magnetic tunnel junctions

An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

STRAINED FERROMAGNETIC HALL METAL SOT LAYER
20210359199 · 2021-11-18 ·

A magnetic memory device includes a spin-orbit torque (SOT) induction structure which may be strained and seedless and formed with a perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed over the SOT induction structure. A spacer layer may decouple layers between the SOT induction structure and the MTJ stack or decouple layers within the MTJ stack. One end of the SOT induction structure may be coupled to a first transistor and another end of the SOT induction structure coupled to a second transistor.

Spinel containing magnetic tunnel junction and method of making the same

A magnetoresistive memory device includes first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes a first texture-breaking nonmagnetic layer including a first nonmagnetic transition metal, a second texture-breaking nonmagnetic layer including a second nonmagnetic transition metal, a magnesium oxide dielectric layer located between the first and second texture-breaking nonmagnetic layers, a reference layer located between the first and second texture-breaking nonmagnetic layers, a free layer located between the first and second texture-breaking nonmagnetic layers, and a spinel layer located between the reference layer and the free layer, and including a polycrystalline spinel material having (001) texture along an axial direction extending between the reference layer and the free layer.

Spin current magnetization rotational element, spin-orbit torque magnetoresistance effect element, and magnetic memory
11222919 · 2022-01-11 · ·

A spin current magnetization rotational element includes: a spin-orbit torque wiring extending in a first direction; and a first ferromagnetic layer laminated in a second direction intersecting with the spin-orbit torque wiring, wherein the first ferromagnetic layer comprises a plurality of ferromagnetic constituent layers and at least one inserted layer sandwiched between adjacent ferromagnetic constituent layers, and polarities of spin Hall angles of two layers, which sandwich at least one of the ferromagnetic constituent layers among the plurality of the ferromagnetic constituent layers, differ.

Megnetoresistive random access memory

A magnetic memory device includes a core element, a free layer surrounding the core element, a barrier layer surrounding the free layer, and a reference layer surrounding the barrier layer. Two ends of the core element are electrically coupled to a first electrode and a second electrode, respectively. A direction of magnetization of the free layer is switchable between a first direction and a second direction under an influence of an electrical current flowing along the core element. The barrier layer includes an electrically insulating material. The reference layer is electrically coupled to a third electrode. A direction of magnetization of the reference layer remains along the first direction or the second direction.